Jordan Carlin
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e78fac1624
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Replace /opt/riscv after merge
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2024-07-25 21:33:31 -07:00 |
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Jordan Carlin
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2f1a101735
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Merge branch 'main' of https://github.com/openhwgroup/cvw into installation
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2024-07-25 21:21:57 -07:00 |
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Jordan Carlin
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22a7ba1889
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Cleanup
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2024-07-25 21:16:00 -07:00 |
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Rose Thompson
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957de2e988
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Merge pull request #896 from davidharrishmc/dev
Updated ImperasTG derived config to turn off peripherals
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2024-07-25 12:20:31 -05:00 |
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David Harris
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cf08d954e1
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Updated ImperasTG derived config to turn off peripherals
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2024-07-25 10:08:34 -07:00 |
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Rose Thompson
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2e4ca4c876
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Merge pull request #895 from davidharrishmc/dev
Fix Issue 894 about floating-point decoding of reserved rm/frm
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2024-07-25 11:51:32 -05:00 |
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David Harris
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7360be1234
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Legalized PMPconfig WARL
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2024-07-25 09:43:54 -07:00 |
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David Harris
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c637e40058
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CHeck legal rnum field when decoding aes64ks1i
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2024-07-25 09:19:23 -07:00 |
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David Harris
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7234abebef
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Issue #894: trap on floating-point ops with reserved rounding modes: detect Zfa flt
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2024-07-25 09:09:13 -07:00 |
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David Harris
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337e40ac1b
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Issue #894: trap on floating-point ops with reserved rounding modes
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2024-07-25 06:59:58 -07:00 |
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Jordan Carlin
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308deba1fb
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Linux readme updates
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2024-07-24 20:19:30 -07:00 |
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Jordan Carlin
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204fd2e9ff
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Update buildroot makefile to test for write access to $RISCV and remove separate sudo/no_sudo versions (just run the makefile as sudo if needed)
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2024-07-24 20:19:30 -07:00 |
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Jordan Carlin
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6d77b22281
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Automatically determine number of threads to use in wally-tool-chain-install
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2024-07-24 20:19:30 -07:00 |
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Jordan Carlin
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602d126776
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Build nproc linux
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2024-07-24 20:19:30 -07:00 |
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Jordan Carlin
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c8519ce54f
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Build testvectors with buildroot
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2024-07-24 20:19:30 -07:00 |
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Jordan Carlin
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04b8739756
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Add cpio to installation for buildroot
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2024-07-24 19:55:18 -07:00 |
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David Harris
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5ac02c79c6
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Merge pull request #892 from ross144/main
Adds synthesizable RVVI FPGA hardware
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2024-07-24 12:21:36 -07:00 |
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Rose Thompson
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5a6e32576d
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Fixed the reset bug in wallyTracer.
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2024-07-24 13:32:46 -05:00 |
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Rose Thompson
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994386f12c
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Removed unused file.
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2024-07-24 13:30:25 -05:00 |
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Rose Thompson
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9053923d92
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2024-07-24 13:14:25 -05:00 |
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Rose Thompson
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13db14db6b
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Factored out the rvvi testbench code into rvvitbwrapper.
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2024-07-24 13:10:57 -05:00 |
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Rose Thompson
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c11036358a
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Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim.
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2024-07-24 12:47:50 -05:00 |
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Rose Thompson
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fb1869fcb9
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Updated verilog-ethernet to remove all verilator warnings or at least suppress them.
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2024-07-24 10:13:03 -05:00 |
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Jordan Carlin
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07ac498623
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Switch to logger function and fix exit codes
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2024-07-23 23:42:03 -07:00 |
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Jordan Carlin
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4c0265f67d
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Update logging grep
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2024-07-23 23:40:42 -07:00 |
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Jordan Carlin
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76277d1e7d
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Fix logging
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2024-07-23 23:40:03 -07:00 |
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Jordan Carlin
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790f566eaa
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Remove hardcoded /opt/riscv
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2024-07-23 23:29:45 -07:00 |
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Rose Thompson
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7960f26e84
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Handled all remaining verilator warnings in the rvvi synth code. Now it's time to take on the verilog-ethernet warnings.
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2024-07-23 17:44:37 -05:00 |
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Rose Thompson
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35efbd6a54
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Changes are confirmed to work on the FPGA.
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2024-07-23 17:39:38 -05:00 |
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Rose Thompson
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bfb3b63a24
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Code cleanup.
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2024-07-23 16:35:05 -05:00 |
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Rose Thompson
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fe9ac36928
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Fixed rvvi csr counting.
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2024-07-23 16:22:23 -05:00 |
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Rose Thompson
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da2511c63c
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Fixed bugs in the rvvi synth logic which encoded csr instructions.
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2024-07-23 16:16:11 -05:00 |
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Rose Thompson
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7bc04702a7
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Down to 3 verilator warnings in rvvisynth and a 40 warnings in verilog-ethernet.
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2024-07-23 13:18:03 -05:00 |
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Rose Thompson
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f20b82b14e
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Moved all rvvi files to rvvi directory.
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2024-07-23 13:03:21 -05:00 |
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Rose Thompson
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d706b5b898
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Fixed bus width error. Have to check this FPGA to make sure this didn't break anything.
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2024-07-23 12:26:03 -05:00 |
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Rose Thompson
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b30656447f
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Resolved more lint errors in the rvvi synthesized hardware.
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2024-07-23 12:23:04 -05:00 |
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Rose Thompson
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ebd8082508
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Merge pull request #891 from davidharrishmc/dev
Increased covergen.py functional coverage to 87.6%
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2024-07-23 09:34:13 -05:00 |
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David Harris
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b7fb786749
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Increased covergen.py functional coverage to 87.6%
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2024-07-23 04:38:13 -07:00 |
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Jordan Carlin
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37046f4ff3
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Fix minimum scipy version for Ubuntu20.04
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2024-07-23 01:03:10 -07:00 |
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Jordan Carlin
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23ceb2532e
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Fix python version for Ubuntu 20.04
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2024-07-23 00:16:27 -07:00 |
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Jordan Carlin
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9dad0aea1d
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Add logs and reduce console output
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2024-07-22 23:13:38 -07:00 |
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Jordan Carlin
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2c08406b7f
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Update python versions
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2024-07-22 23:12:48 -07:00 |
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Jordan Carlin
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a2b9e34682
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Use requirements file for pip packages
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2024-07-22 23:12:27 -07:00 |
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Jordan Carlin
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f20edbf22e
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Add DEBIAN_FRONTEND=noninteractive to apt
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2024-07-22 23:11:33 -07:00 |
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Jordan Carlin
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23b7d2059f
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Update section header function usage
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2024-07-22 23:10:45 -07:00 |
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Rose Thompson
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c6c2240630
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2024-07-22 17:48:34 -05:00 |
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Rose Thompson
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5381e1f395
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Updated for a better ILA rvvi debugger.
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2024-07-22 17:44:04 -05:00 |
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Rose Thompson
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3c06556833
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Updated the verilog-ethernet repo to remove most of the warnings. Updated the fpga constraints so the ILA is more useful when using RVVI.
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2024-07-22 16:12:06 -05:00 |
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Rose Thompson
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35e69944fa
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Cleaned up rvvisynth.sv
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2024-07-22 12:22:41 -05:00 |
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Rose Thompson
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efa99940c5
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Added option to use rvvi ila
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2024-07-22 12:19:37 -05:00 |
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