Diego Herrera Vicioso
d29dc30288
Excluded coverage for impossible cases in wficountreg and status.MPRV
2023-04-24 02:06:53 -07:00
David Harris
52f49ed24d
Fault on writes to odd-numbered PMPCFG in RV64
2023-04-22 15:32:39 -07:00
David Harris
3b299fb77a
Removed unproven fdivsqrt exclusion
2023-04-22 15:27:05 -07:00
David Harris
086556310c
Attempted to cause interrupt during fdivsqrt. Fixed enabling fpu in fpu.S. Fdivsqrt exclusions for coverage.
2023-04-22 12:22:45 -07:00
David Harris
063e41806e
Fixted syntax error in exclusion. Arbitrarily picked -e 1; fix if this isn't right
2023-04-22 10:07:48 -07:00
David Harris
8a59a4ce94
fdivsqrt cleanup
2023-04-20 17:35:01 -07:00
David Harris
86107e6136
continued cleanup
2023-04-20 16:48:23 -07:00
David Harris
33c0f64457
Reordered fdivsqrtpreproc to follow logic
2023-04-20 16:38:47 -07:00
David Harris
2c47268f50
Started fdivsqrtpreproc flow organization
2023-04-20 16:25:19 -07:00
David Harris
f2ae770e17
Fmv h/q comments in controller
2023-04-20 16:24:58 -07:00
David Harris
b9d641f13a
Merge pull request #256 from cturek/main
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Simplifying fds to follow diagram
2023-04-20 16:07:22 -07:00
David Harris
3a8d2db194
Merge pull request #262 from SydRiley/main
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removed comments for fixed bugs in fpu, increased coverage in fpu, ifu, and lsu: fpu from 93.51% to 93.62%, ifu from 78.56% to 78.75%, lsu from 88.96% to 88.98%
2023-04-19 14:49:50 -07:00
Sydeny
a132ffa7f7
removed comments for fixed bugs in fpu, increased coverage: fpu from 93.51% to 93.62%, ifu from 78.56% to 78.75%, lsu from 88.96% to 88.98%
2023-04-19 13:30:12 -07:00
Alec Vercruysse
faaf266558
CacheFSM logic simplification for AMO operations
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Ran this by Ross.
2023-04-19 01:34:01 -07:00
Alec Vercruysse
de93bd6937
D$ scope-specific coverage exclusions (I$ logic that never fires)
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The InvalidateCache signal in the D$ is for I$ only, which
causes some coverage issues that need exclusion.
Another manual exclusion is due to the fact that D$ writeback, flush,
write_line, or flush_writeback states can't be cancelled by a flush,
so those transistions are excluded.
There is some other small stuff to review (logic simplification,
or an exclusion pragma if removing the redundent logic would
make it harder to understand the code, as is the case in the
FlushAdrCntEn assign statement, in my opinion).
2023-04-19 01:34:01 -07:00
Cedar Turek
49356aa4ca
created fdivsqrtcycles, moved cycles calculation from FSM to preproc
2023-04-18 16:14:45 -07:00
Cedar Turek
b1dd1a627f
gave integer bits to D instead of adding manually everywhere
2023-04-18 15:41:04 -07:00
Cedar Turek
914baf6bb1
moved D flop to preproc
2023-04-18 15:14:17 -07:00
Sydeny
ee5deb10a7
Merge branch 'main' of https://github.com/openhwgroup/cvw into main
2023-04-17 13:51:16 -07:00
David Harris
a413b5c6ca
Merge pull request #251 from masonadams25/main
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Removed redundent expression to increase coverage
2023-04-17 12:37:27 -07:00
Mason Adams
56575cb45e
Removed redundent expression to increase coverage
2023-04-17 14:13:26 -05:00
David Harris
64fe318cb0
merged coverage exclusions
2023-04-17 10:17:48 -07:00
Diego Herrera Vicioso
16fd17be39
Added test coverage for reads to HPM counters and added exclusions for impossible cases in rv64gc
2023-04-15 23:13:39 -07:00
Sydeny
0dc50536ef
trimming comments on fctrl bug fixes
2023-04-15 00:48:32 -07:00
Ross Thompson
30e3d2cdce
Merge pull request #233 from AlecVercruysse/coverage3
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Full I$ coverage
2023-04-14 22:15:11 -05:00
Alec Vercruysse
4d9aa72877
replace instances of code duplication for i$ exclusions w/commands
2023-04-14 17:10:39 -07:00
Limnanthes Serafini
49e025bd48
Final small fix
2023-04-14 14:15:52 -07:00
Limnanthes Serafini
2c20079a46
indent fix
2023-04-14 14:14:34 -07:00
Limnanthes Serafini
b3976daccd
More cleanup
2023-04-13 21:34:50 -07:00
Limnanthes Serafini
b80a540c73
More cleanup
2023-04-13 21:02:30 -07:00
Limnanthes Serafini
53847269da
More changes
2023-04-13 21:02:15 -07:00
Limnanthes Serafini
0b6ce1b031
Some cleanup
2023-04-13 21:01:57 -07:00
David Harris
48de682ea8
Merged coverage-exclusions
2023-04-13 18:15:23 -07:00
David Harris
5066cd99ab
Merge pull request #237 from SydRiley/main
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fctrl coverage at 100% after removing redundancies from conditionals
2023-04-13 17:10:46 -07:00
Limnanthes Serafini
95586abe09
Merge branch 'cachesim' of https://github.com/AlecVercruysse/cvw into cachesim
2023-04-13 16:54:16 -07:00
Limnanthes Serafini
034c289a36
Misc typo and indent fixing.
2023-04-13 16:54:15 -07:00
David Harris
11434f05e2
Starting fdivsqrt cleanup
2023-04-13 16:53:33 -07:00
Sydeny
2b8891cefd
Updating changes to fctrl.sv to reach 100% coverage. Excluding un-used sources of instructions for the ifu.
2023-04-13 16:27:53 -07:00
Alec Vercruysse
680aee7e07
Merge branch 'main' into coverage3
2023-04-12 16:00:15 -07:00
Alec Vercruysse
01f2417524
cachefsm exclude icache logic without code reuse
2023-04-12 15:57:45 -07:00
Alec Vercruysse
cc3b2bf435
Cachefsm gate LRUWriteEn with ~FlushStage
2023-04-12 13:32:36 -07:00
Sydeny
f9566299a0
fctrl coverage at 100% after removing redundancies from conditional statements
2023-04-12 13:07:30 -07:00
Ross Thompson
10be07857c
Merge pull request #229 from davidharrishmc/dev
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Turned on SVADU_SUPPORTED in rv32/64gc wally-config and in imperas.ic…
2023-04-12 12:21:03 -05:00
Alec Vercruysse
1cb6e1751b
Merge branch 'main' into coverage3
2023-04-12 09:34:09 -07:00
David Harris
6b05a71152
Removed unnecessary start term from initialization muxes to simplify and improve coverage
2023-04-12 03:34:01 -07:00
David Harris
463a1e2b33
Fixed fdivsqrt to avoid going from done to busy without going through idle first
2023-04-12 02:48:40 -07:00
Limnanthes Serafini
65d29306ef
Merge branch 'openhwgroup:main' into cachesim
2023-04-12 01:34:45 -07:00
Alec Vercruysse
0ed3e80ee0
only assign ClearDirtyWay for read-write caches
2023-04-12 01:15:35 -07:00
Alec Vercruysse
4cbb9bcec6
refactor cachefsm to get full coverage
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I had to exclude i$ states in coverage-exclusions-rv64gc.do,
but it's referred to by scope, which should be pretty robust
2023-04-12 01:15:35 -07:00
Alec Vercruysse
a1bbcd5e8a
Coverage and readability improvements to LRUUpdate logic
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The genvar stuff was switched to readable names to make it easier
to understand for the first time. In the LRUUpdate logic for loop,
a special case was added for simpler logic in the case of the root
node, to hit coverage.
2023-04-12 01:15:35 -07:00