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4,290 Commits 4 Branches 2 Tags 53 MiB
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106 Commits

Author SHA1 Message Date
Kip Macsai-Goren
e603973dff added xlen and endianness test edits. xlen passes but endinanness still won't make 2022-09-26 05:03:19 +00:00
Kip Macsai-Goren
0cc7f5719c ported endianness tests to 32 bits (not tested in regression yet) 2022-09-18 00:10:29 +00:00
David Harris
898dbc8e74 Completed PLIC-S tests. Regression working. This completes peripheral tests. 2022-08-03 09:33:56 -07:00
David Harris
4fb467ee8a Debugging plic-s test 2022-08-03 13:21:09 +00:00
David Harris
7e5b78f240 plic-s debug 2022-08-03 12:33:09 +00:00
David Harris
cab0349701 Started plic-s tests 2022-08-03 03:48:08 +00:00
David Harris
93d7d7179e Added parity and stop bit tests to UART 2022-07-28 04:35:51 +00:00
David Harris
429bdae1c4 Fixed UART reference output 2022-07-27 22:16:38 +00:00
David Harris
b08c87cb47 Finished UART test 2022-07-27 04:06:59 +00:00
slmnemo
7348af7fd5 Updated reference file for UART test 2022-07-26 09:39:31 -07:00
slmnemo
5218865a7f Committing changes made to UART test 2022-07-26 09:14:40 -07:00
slmnemo
bfced6bfe8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-22 17:13:38 -07:00
slmnemo
ca4511b6dc Fixed UART FIFO bugs and added FIFO tests 2022-07-22 17:13:19 -07:00
Daniel Torres
4da96c5791 fixed 32priv tests, now passing 2022-07-22 15:35:20 -07:00
Daniel Torres
24828db612 changes to test.vh for compatability 2022-07-22 15:00:48 -07:00
Daniel Torres
4198145ce2 added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail 2022-07-22 14:58:55 -07:00
slmnemo
141f2a40e4 UART updates and PMA fix 2022-07-22 14:49:03 -07:00
slmnemo
9cca567136 Added test comments to reference output 2022-07-22 12:35:59 -07:00
Daniel Torres
0e75142ef4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-22 11:16:09 -07:00
Daniel Torres
95fdd408ee commiting current changes to riscof wally tests 2022-07-22 11:14:04 -07:00
slmnemo
d38369e8bf Added new PLIC and UART tests 2022-07-22 07:12:55 -07:00
slmnemo
df568fd202 Added PLIC and UART tests and new functions to the test library 2022-07-22 07:10:39 -07:00
slmnemo
37bf837d48 fixed GPIO test by adding a new function to clear PLIC interrupts 2022-07-19 08:59:16 -07:00
slmnemo
e190aeb14b Fixed error in gpio test 2022-07-08 02:27:16 -07:00
Katherine Parry
7771f7b3eb added load and store test 2022-07-07 21:48:51 +00:00
slmnemo
6b2125ab0e Fixed discrepancies between GPIO tests and book and removed extra unused code from CLINT tests. 2022-07-05 18:21:17 -07:00
slmnemo
f21c3114fd Added termination line to CLINT test 2022-06-27 20:16:29 -07:00
slmnemo
228028c837 Add CLINT tests from book 2022-06-27 20:09:58 -07:00
slmnemo
033ec135f8 Added reset read testcodes to GPIO 2022-06-27 18:56:35 -07:00
slmnemo
cb8ae72326 Fixed error in GPIO signature 2022-06-23 14:12:28 -07:00
David Harris
db459c3380 GPIO tests 2022-06-23 21:06:11 +00:00
slmnemo
d86a65daf0 Updating new GPIO tests 2022-06-23 13:22:00 -07:00
slmnemo
80a57d0469 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-06-21 02:16:26 -07:00
slmnemo
b2cea45de0 Added rudimentary GPIO test according to testplans in chapter 15 2022-06-21 02:16:21 -07:00
Katherine Parry
03d823f5d7 added fld in rv32 - needs testing 2022-06-20 22:53:13 +00:00
DTowersM
b586e3af37 added some comments to help debuggers in the future 2022-06-10 01:44:52 +00:00
DTowersM
4e5d7ec3d6 changed DCACHE_LINELENINBITS and ICACHE_LINELENINBITS to 512, had to modigy the wfi test to increase timee before interupt to mantain compatability 2022-06-10 00:37:53 +00:00
Kip Macsai-Goren
553e7bfeb9 Fixed priv test reference outputs to have the right number of "DEADBEEF"s (1024) 2022-05-12 22:30:14 +00:00
David Harris
73a84f28b9 Moved some privileged tests to be simulated. 2022-05-12 04:45:41 +00:00
David Harris
c100c9893b wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts 2022-05-05 14:37:21 +00:00
Kip Macsai-Goren
8f748c4014 clarified some trap causing functions to use zzero register rather than li [reg] 0x0. Also updated signatures' tvals 2022-05-04 23:01:23 +00:00
Kip Macsai-Goren
88173b8bb3 added explicit clears to mstatus.mie 2022-05-04 23:00:17 +00:00
Kip Macsai-Goren
6a182efe0f Updated test libraries to reflect variable name changes 2022-05-04 21:39:36 +00:00
Kip Macsai-Goren
6a372b1a1d renamed test_loop_setup to run_test_loop 2022-05-04 21:39:09 +00:00
Kip Macsai-Goren
393edc9fd8 renamed debug to extended signature 2022-05-04 21:38:37 +00:00
Kip Macsai-Goren
0f70e48b6b updated makefrag and tests.vh to reflect removed tests, new names 2022-05-04 21:20:25 +00:00
Kip Macsai-Goren
923cbc59a3 removed fp-diabled test and leftover mimpid test 2022-05-04 21:20:25 +00:00
Kip Macsai-Goren
3cab9f0234 removed instruction misaligned tests from trap tests, signatures 2022-05-04 21:20:25 +00:00
Kip Macsai-Goren
8c96672080 renamed all tests to have lower-case titles except for WALLY 2022-05-04 21:20:25 +00:00
Kip Macsai-Goren
208827502e general test cleanup of comments and old files 2022-04-29 19:55:29 +00:00