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Author	SHA1	Message	Date
Jordan Carlin	1a205412cb	csh fixes	2024-07-26 22:35:10 -07:00
Jordan Carlin	ea16f132f5	Create LD_LIBRARY_PATH if blank	2024-07-26 22:35:07 -07:00
Jordan Carlin	47f4b563a1	Clean up install script comments	2024-07-26 22:35:02 -07:00
Jordan Carlin	0266743582	Add buildroot to wally-tool-chain-install	2024-07-26 22:34:55 -07:00
Jordan Carlin	ab885287bb	Actually fix buildroot makefile	2024-07-26 22:34:46 -07:00
Jordan Carlin	ec7e3d4f3b	Remove ftp from installation	2024-07-26 22:34:34 -07:00
Jordan Carlin	07113eed9f	Add libncurses* to Ubuntu for Vivado	2024-07-26 10:57:41 -07:00
Jordan Carlin	518650a756	Attempt to fix buildroot makefile	2024-07-25 22:26:34 -07:00
Jordan Carlin	fed45d9eb6	Move verilator stack limit to setup.sh/csh insteaed of site-setup	2024-07-25 21:35:52 -07:00
Jordan Carlin	e851812608	Replace /opt/riscv after merge	2024-07-25 21:33:31 -07:00
Jordan Carlin	42a9bbf28d	Merge branch 'main' of https://github.com/openhwgroup/cvw into installation	2024-07-25 21:21:57 -07:00
Jordan Carlin	22d2077006	Cleanup	2024-07-25 21:16:00 -07:00
Jacob Pease	3975f60299	Added carriage returns to line feed characters. UART messages print properly now.	2024-07-25 13:05:57 -05:00
Jacob Pease	a36e846b02	Changed formatting and added new UART divsor calculation from OpenSBI.	2024-07-25 13:04:27 -05:00
Rose Thompson	6f78a60468	Merge pull request #896 from davidharrishmc/dev ... Updated ImperasTG derived config to turn off peripherals	2024-07-25 12:20:31 -05:00
David Harris	da853b45e6	Updated ImperasTG derived config to turn off peripherals	2024-07-25 10:08:34 -07:00
Rose Thompson	6496454054	Merge pull request #895 from davidharrishmc/dev ... Fix Issue 894 about floating-point decoding of reserved rm/frm	2024-07-25 11:51:32 -05:00
David Harris	faa1378920	Legalized PMPconfig WARL	2024-07-25 09:43:54 -07:00
David Harris	d5af25ffbf	CHeck legal rnum field when decoding aes64ks1i	2024-07-25 09:19:23 -07:00
Jacob Pease	336a413f31	Added ability to split boot.memfile into boot.mem and data.mem.	2024-07-25 11:19:15 -05:00
David Harris	5bf7250687	Issue #894: trap on floating-point ops with reserved rounding modes: detect Zfa flt	2024-07-25 09:09:13 -07:00
David Harris	f7dd49cc6c	Issue #894: trap on floating-point ops with reserved rounding modes	2024-07-25 06:59:58 -07:00
Jacob Pease	0dae881a0d	Fixed SDCCLK name discrepency.	2024-07-24 22:48:31 -05:00
Jacob Pease	ebdf25a53b	Commented out references to old axi IP from wally.tcl.	2024-07-24 22:47:15 -05:00
Jacob Pease	2caf9e93be	Removed old axi IP from fpga Makefile. Added sed for data.mem file loaded into uncore ram.	2024-07-24 22:46:24 -05:00
Jacob Pease	d15be492cb	Masked lower byte when writing to DLL.	2024-07-24 22:44:27 -05:00
Jacob Pease	286d80de7e	Initialized UART with Arty frequency and baud rate. Will make this dynamic in the future	2024-07-24 22:43:47 -05:00
Jacob Pease	0107a400d1	Added uart header to gpt.c.	2024-07-24 22:43:16 -05:00
Jordan Carlin	4b86f85904	Linux readme updates	2024-07-24 20:19:30 -07:00
Jordan Carlin	a9cd457536	Update buildroot makefile to test for write access to $RISCV and remove separate sudo/no_sudo versions (just run the makefile as sudo if needed)	2024-07-24 20:19:30 -07:00
Jordan Carlin	676c6b88a0	Automatically determine number of threads to use in wally-tool-chain-install	2024-07-24 20:19:30 -07:00
Jordan Carlin	e6b3257862	Build nproc linux	2024-07-24 20:19:30 -07:00
Jordan Carlin	85b98af958	Build testvectors with buildroot	2024-07-24 20:19:30 -07:00
Jordan Carlin	bbf90b1f4b	Add cpio to installation for buildroot	2024-07-24 19:55:18 -07:00
David Harris	2c7bc7038e	Merge pull request #892 from ross144/main ... Adds synthesizable RVVI FPGA hardware	2024-07-24 12:21:36 -07:00
Rose Thompson	ce61429bdf	Fixed the reset bug in wallyTracer.	2024-07-24 13:32:46 -05:00
Rose Thompson	5cae55561e	Removed unused file.	2024-07-24 13:30:25 -05:00
Rose Thompson	df88939bcb	Merge branch 'main' of https://github.com/openhwgroup/cvw	2024-07-24 13:14:25 -05:00
Rose Thompson	d0a5b278b7	Factored out the rvvi testbench code into rvvitbwrapper.	2024-07-24 13:10:57 -05:00
Rose Thompson	b1a711ae0f	Converted fpga's rvvi from a config option to a testbench/fpga top level parameter and is envoked by passing --rvvi to wsim.	2024-07-24 12:47:50 -05:00
Rose Thompson	27f89fcdbd	Updated verilog-ethernet to remove all verilator warnings or at least suppress them.	2024-07-24 10:13:03 -05:00
Jordan Carlin	bb5c9f9ead	Switch to logger function and fix exit codes	2024-07-23 23:42:03 -07:00
Jordan Carlin	d08deddcc4	Update logging grep	2024-07-23 23:40:42 -07:00
Jordan Carlin	121ee51503	Fix logging	2024-07-23 23:40:03 -07:00
Jordan Carlin	47452ddaaa	Remove hardcoded /opt/riscv	2024-07-23 23:29:45 -07:00
Rose Thompson	9404a339ee	Handled all remaining verilator warnings in the rvvi synth code. Now it's time to take on the verilog-ethernet warnings.	2024-07-23 17:44:37 -05:00
Rose Thompson	6c212ebf0e	Changes are confirmed to work on the FPGA.	2024-07-23 17:39:38 -05:00
Jacob Pease	f1cc7dd5a3	Fixed verilog bugs.	2024-07-23 17:26:39 -05:00
Jacob Pease	dcb2edf888	Fixed syntax bugs. inline functions are now static and in the spi.h header.	2024-07-23 17:00:32 -05:00
Rose Thompson	e8e71ad643	Code cleanup.	2024-07-23 16:35:05 -05:00