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Author	SHA1	Message	Date
Ross Thompson	e488ee7225	Correctly sending the ethernet frame on a mismatch. Now just need to get vivado to actually trigger.	2024-07-09 14:16:13 -05:00
Ross Thompson	fd170a6583	Getting closer.	2024-07-09 14:09:56 -05:00
Ross Thompson	bf69a2e1cd	Updated to use the newest imperasDV.	2024-07-09 12:30:18 -05:00
Ross Thompson	dc97ee5f82	Have some sample code which I know works transmisting a packet.	2024-07-02 09:12:34 -07:00
Ross Thompson	ccf4bb8ddc	Maybe have the incircuit trigger working.	2024-06-26 16:15:46 -07:00
Ross Thompson	612a281f62	Added module to receive ethernet frame and trigger the ila.	2024-06-26 11:05:31 -07:00
Ross Thompson	74189e1e4b	Have vivado triggering the ILA after the mismatch but the latency is way too long.	2024-06-25 17:04:14 -07:00
Ross Thompson	fa26c9a8b5	Added pipe to vivado to create ila trigger from rvvidaemon.	2024-06-25 13:07:46 -07:00
Ross Thompson	249d58244a	It's working!!!!!!	2024-06-20 15:48:30 -07:00
Ross Thompson	1c6ebb86a3	Added some debug code to count frames sent to the ethernet mac and frames sent to the phy. ... Removed the external reset of the phy and now it always reliably starts in the same way. The first 0x117 frames are always captured.	2024-06-20 12:54:12 -07:00
Ross Thompson	2581ea0b74	Found the actual bug. Once the ethernet transmit fifo was full the rvvi packetizer was not correctly marking the end of the frame. First Last was held for too many cycles. Second it was assert on cycles when Valid was not high. Simulation reproduced the FPGA corrupted frames and then with the fix showed working frames.	2024-06-18 16:48:49 -07:00
Ross Thompson	00e0549c36	I know what is wrong now. The ethernet device IP is not correctly generating the mii nibble stream. Some nibbles are dropped in each 4-byte word. ... The default input interface to the interface is 8-bit and I used 32-bit. I suspect there is a bug in the implementation for non-8-bit interfaces.	2024-06-18 07:44:19 -07:00
Ross Thompson	93829ce509	Success! We have some instructions comparing across the FPGA and IDV! ... However I'm still losing ethernet frames.	2024-06-17 13:41:40 -07:00
Ross Thompson	598770da51	Getting much closer to a working version.	2024-06-17 12:37:10 -07:00
Ross Thompson	cccb40e4b5	Got the tracer not overrunning ethernet buffers so frames are not being dropped.	2024-06-17 09:16:24 -07:00
Ross Thompson	82b54c0887	Got IDV properly initalized.	2024-06-17 09:15:59 -07:00
Ross Thompson	47523c97ac	Getting closer to figuring out the lost ethernet frame bugs.	2024-06-13 15:46:54 -07:00
Ross Thompson	c9f51df34a	Fixed bug in rvvi reset.	2024-06-12 14:47:32 -07:00
Ross Thompson	323dbd348e	Progress.	2024-06-12 12:54:21 -07:00
Ross Thompson	f5d4db68b1	Modified rvvidaemon to populate a struct with all the relavent fields.	2024-06-12 08:56:16 -07:00
Ross Thompson	3e7d07dfb6	Better.	2024-06-11 17:14:59 -07:00
Ross Thompson	8bce2fc739	Getting closer.	2024-06-11 16:21:53 -07:00
Ross Thompson	c9f3da51cb	getting closer to full reconstruction of rvvi.	2024-06-11 15:35:35 -07:00
Ross Thompson	3d9f796f21	Better parsing of rvvi.	2024-06-11 14:36:34 -07:00
Ross Thompson	563980443a	Merge branch 'main' into rvvi	2024-06-10 18:10:23 -07:00
Ross Thompson	49912589f5	Added rvviApi.h to rvvidaemon.	2024-06-10 17:57:24 -07:00
Ross Thompson	e16cf9d739	Added Makefile to compile rvvidaemon	2024-06-10 16:56:53 -07:00
Rose Thompson	72c1374d9c	Minor code cleanup.	2024-06-04 15:11:57 -05:00
Rose Thompson	f0ed780745	progress.	2024-06-04 15:11:03 -05:00
Rose Thompson	07d66c246c	Update.	2024-06-04 11:59:17 -05:00
Rose Thompson	08ff88f428	On the way towards complete reconstruction of the RVVI trace.	2024-06-04 11:47:46 -05:00
Rose Thompson	fc62f80407	Closer to fully working hardware tracer.	2024-06-04 11:31:05 -05:00
Rose Thompson	80f98b3223	now have a working ethernet daemon to collect frames and partially decode into RVVI.	2024-06-04 10:20:51 -05:00
Rose Thompson	dc904cdbbb	The ethernet frame is mostly formatted correctly. Just need to reverse the byte order in the Ethernet length/type field.	2024-06-03 18:10:25 -05:00
Rose Thompson	0ca10e7ee2	Last of the branch predictor signal name updates.	2024-06-02 17:01:51 -05:00
Rose Thompson	04744032d8	Updated more signal names to match book.	2024-06-02 16:59:11 -05:00
Rose Thompson	b45b7ff7d6	Signal name changes to match book.	2024-06-02 16:32:25 -05:00
Rose Thompson	731e1fe08f	Updated spill logic to reflect changes in textbook.	2024-06-02 15:48:42 -05:00
Rose Thompson	3da62558ec	Updated readme.	2024-06-01 11:12:30 -05:00
Rose Thompson	2382677f8f	Got the directory mode wsim working!	2024-06-01 10:56:37 -05:00
Rose Thompson	224b8469ab	Updated readme to reflect changes to wsim.	2024-06-01 09:58:10 -05:00
Rose Thompson	a78093274c	Simplified wsim so it automatically figures out if the second parameter is a testsuite or an elf file.	2024-06-01 09:56:50 -05:00
Rose Thompson	2a6c5a158f	Merge branch 'main' of https://github.com/openhwgroup/cvw	2024-06-01 09:50:18 -05:00
Rose Thompson	a830bd57f0	Have to reverse the byte order for ethernet frame length.	2024-05-31 17:46:43 -05:00
Rose Thompson	e05ebc30b8	Almost worked out the bugs in packetizer.	2024-05-31 16:48:41 -05:00
Rose Thompson	9ed78b5f08	Merge pull request #818 from JacobPease/main ... Added true bootloader to fpga/zsbl directory.	2024-05-31 15:34:08 -05:00
Jacob Pease	7a417d7a6c	Added true bootloader to fpga/zsbl directory.	2024-05-31 15:28:25 -05:00
Rose Thompson	0dccc6051d	draft of receiving code to unpack the ethernet frames into rvvi.	2024-05-31 13:55:25 -05:00
Rose Thompson	1df3e5239a	This is great. The FPGA is able to send ethernet frames consisting of the RVVI data to the host computer. ... wireshark is able to capture the frames and they match the expected data!	2024-05-30 17:57:28 -05:00
Rose Thompson	6a4c8667df	Added new signals to ILA to debug the RVVI tracer. ... The tracer appears to be stuck and the CPU is never getting out of (into reset).	2024-05-30 16:43:25 -05:00