Jordan Carlin
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569ccfd829
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Update riscv-arch-test submodule
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2024-06-18 23:34:02 -07:00 |
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Jordan Carlin
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f410bbb79e
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Use Zfa tests from riscv-arch-test instead of wally-riscv-arch-test
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2024-05-21 00:04:27 -07:00 |
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Quswar Abid
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f999ccadf4
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/cad/mentor/questa_sim-2023.4/questasim is fixed, relative paths to design and testbench files are fixed, and RISCV-DV submodule is updated back to the latest commit on master branch
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2024-04-26 15:55:39 -07:00 |
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David Harris
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3950588b8c
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Brought subrepos up to date
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2024-04-24 07:36:42 -07:00 |
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Quswar Abid
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6f16b7e0c9
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updated the submodules -> riscv-arch-tests and riscv-dv
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2024-04-17 10:25:36 -07:00 |
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David Harris
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fec160d6f9
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Updated coremark to use wsim
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2024-04-06 21:38:44 -07:00 |
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Rose Thompson
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6110799a1e
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Updated the wally rv32 priv tests to not use sail.
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2024-02-16 11:39:06 -06:00 |
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David Harris
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430d495ce5
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Updated to latest riscv-arch-test
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2023-12-31 10:04:20 -08:00 |
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Rose Thompson
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e38b43ae73
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Replaced the git@github with hptts:github submodule for ahbsdc which I hope will fix Lee's clone issue
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2023-12-11 14:12:38 -06:00 |
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David Harris
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d8186b9f58
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Swap in branch predictor simulator handling compressed instruction offsets
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2023-11-21 16:42:41 -08:00 |
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David Harris
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93a0db1fca
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swapped branch predictor simulator
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2023-11-21 15:02:09 -08:00 |
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David Harris
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2b2016271a
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repo cleanup and start to add CMO tests
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2023-11-20 23:41:36 -08:00 |
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David Harris
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8cb433cb66
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Commented IROM preloading
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2023-11-19 19:33:57 -08:00 |
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Jacob Pease
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a1e7158bd9
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Merge branch 'main' of github.com:openhwgroup/cvw
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2023-11-18 19:20:48 -06:00 |
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Jacob Pease
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38cf7f0fb7
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ahbsdc submodule actually added this time.
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2023-11-16 17:46:48 -06:00 |
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Jacob Pease
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9df87872ef
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Deleted vivado-risc-v directory and added ahbsdc.
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2023-11-16 15:13:12 -06:00 |
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David Harris
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7b2bb86ced
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changed to head of riscv-arch-test
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2023-11-15 09:48:13 -08:00 |
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David Harris
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90cf128349
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Added back riscv-arch-test fresh
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2023-11-15 05:48:33 -08:00 |
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David Harris
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18c29dd7d0
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Removed riscv-arch-test submodule that appears corrupted
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2023-11-15 05:46:38 -08:00 |
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David Harris
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8ba0336c6f
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Removed unused addins, cleaned up configuration to support half precision on RV64gc, gate unused hazard inputs to reduce critical path in rv32e
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2023-11-14 11:01:58 -08:00 |
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naichewa
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75f1c07022
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merge main, pull /A/ tests
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2023-11-03 13:16:19 -07:00 |
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Ross Thompson
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b1f7a5768f
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Removed all old references to the old flash card controller.
Added git submodule for the flash card in addins.
Replicated flash card top level for our changes into the fpga/src directory.
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2023-07-24 15:45:57 -05:00 |
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Ross Thompson
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026570d3da
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Added new submodule for digilent fpga boards.
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2023-07-17 16:25:37 -05:00 |
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Victor Clements
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9461b9db7e
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pulling in FreeRTOS/kernel Submodule
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2023-06-13 10:41:18 -07:00 |
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David Harris
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98a44fd3bd
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wally installation improvements: latest main branch of riscv-arch-test, updated install script
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2023-05-10 08:23:55 -07:00 |
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Ross Thompson
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f067935eed
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Added Yujun Lin's branch predictor simulator. This is a C baseline module for common branch predictor algorithms.
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2023-03-07 10:49:59 -06:00 |
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David Harris
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906e74dac2
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Pulled to latest commit of riscv-arch-test
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2023-02-28 15:03:59 -08:00 |
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James Stine
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8b4c3920db
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Update Appendix D + wrapped memories
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2023-01-28 19:46:43 -06:00 |
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David Harris
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5df4679bcb
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Removed old link to imperas-riscv-tests
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2023-01-26 14:53:25 -08:00 |
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James Stine
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a5d402c6ce
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This adds the Dockerfile for those who might be interested in building a docker container for Wally
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2023-01-23 17:29:58 -06:00 |
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David Harris
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1ec62606f9
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sram1p1rw cleanup
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2022-12-20 02:57:51 -08:00 |
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Ross Thompson
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fc05e27416
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Updated riscv arch test removed misaligned1.
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2022-12-04 00:18:10 +00:00 |
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David Harris
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f326b18af6
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embench cleaned up
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2022-09-08 11:38:01 -07:00 |
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Katherine Parry
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655e2d3810
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merged radix-2 sqrt into divider - doesnt work yet
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2022-07-23 00:41:18 +00:00 |
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slmnemo
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df568fd202
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Added PLIC and UART tests and new functions to the test library
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2022-07-22 07:10:39 -07:00 |
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Daniel Torres
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c29a60c198
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changed gitignore, updated version of arch tests on main build
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2022-07-21 21:10:15 -07:00 |
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Katherine Parry
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fbe8bb2298
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radix-4 division integrated into srt - not tested
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2022-07-21 19:38:06 +00:00 |
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Daniel Torres
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e46e96e080
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changed the default branch of embench
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2022-07-21 10:14:05 -07:00 |
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David Harris
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e22d6a2f9a
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Removed Sky130 libraries
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2022-07-06 13:50:11 +00:00 |
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Katherine Parry
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03d823f5d7
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added fld in rv32 - needs testing
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2022-06-20 22:53:13 +00:00 |
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Madeleine Masser-Frye
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59a514ae81
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remove run deletion with wally synthesis
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2022-06-17 19:45:38 +00:00 |
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DTowersM
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7c0f4dd954
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-13 23:34:35 +00:00 |
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DTowersM
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39ed36d0ba
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added back working coremark in benchmarks/riscv64-bcoremarkdirectory, experimental simplifications are in benchmarkscoremark/ but this doesn't currently work (some type of c bug)
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2022-06-13 23:23:57 +00:00 |
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Katherine Parry
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5f7072bd96
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postprocessing unit created and passing all tests
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2022-06-13 22:47:51 +00:00 |
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Madeleine Masser-Frye
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5a9f1a3970
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update
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2022-06-03 21:17:50 +00:00 |
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Katherine Parry
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559c0c278e
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added unpackinput.sv
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2022-05-31 16:18:50 +00:00 |
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Madeleine Masser-Frye
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d5e0eb9eb4
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added optimized area plotting
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2022-05-30 18:54:02 +00:00 |
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Katherine Parry
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835a4e4606
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fixed lint error
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2022-05-28 10:20:13 -07:00 |
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Madeleine Masser-Frye
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4ed7283ad1
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fixed normalization vertical axes, added TechSpecs type
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2022-05-28 04:57:18 +00:00 |
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Katherine Parry
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d5c249bf71
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unpacker adds 1 to denorm expoents
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2022-05-27 14:37:10 -07:00 |
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