David Harris
ed1aaa6c8f
Comment cleanup in subcachelineread
2023-01-28 11:00:05 -08:00
David Harris
1b0b9314c4
removed unused memory model
2023-01-28 10:58:36 -08:00
David Harris
a99fc74976
Removed integer from localparams
2023-01-27 14:40:06 -08:00
Ross Thompson
07308e2c14
Removed mark_debug from all source code.
2023-01-20 18:47:36 -06:00
Ross Thompson
3d71d0196c
Updated figure cache references.
2023-01-20 15:01:54 -06:00
Ross Thompson
b1f3bd566c
Formatting.
2023-01-20 13:13:05 -06:00
Ross Thompson
f78bfc4940
Formatting.
2023-01-20 13:09:42 -06:00
Ross Thompson
c7f4970597
Formatting.
2023-01-20 13:05:10 -06:00
Ross Thompson
6142c96946
Reformatting cachefsm.
2023-01-20 12:49:55 -06:00
Ross Thompson
7e96f3e8f7
Formatting.
2023-01-20 12:41:57 -06:00
Ross Thompson
eb19b1b499
Imperas found a bug with the Fence.I instruction.
...
If a fence.i directly followed a store miss, the d$ would release Stall during the cache line write.
Then transition to ReadHold. This cause the d$ flush to go high while in ReadHold. The solution is
to ensure the cache continues to assert Stall while in WriteLine state.
There was a second issue also. The D$ flush asserted FlushD which flushed the I$ invalidate.
Finally the third issue was CacheEn from the FSM needs to be asserted on an InvalidateCache.
2023-01-20 10:17:21 -06:00
David Harris
364cf97c34
cache cleanup
2023-01-14 19:43:29 -08:00
David Harris
7d93659f6b
changed name to CORE-V-WALLY
2023-01-11 15:15:08 -08:00
David Harris
b911056e66
Changed Wally to CORE-V Wally
2023-01-11 14:03:44 -08:00
David Harris
e92cffbb5e
Changed MIT license to Solderpad License
2023-01-10 11:35:20 -08:00
David Harris
a757dcb5bd
Cache code cleanup
2023-01-07 15:49:18 -08:00
David Harris
989b209a60
Cache code cleanup
2023-01-07 15:46:23 -08:00
David Harris
9f7bef7921
Cache code cleanup
2023-01-07 15:44:44 -08:00
David Harris
ec0e9b117b
Cache code cleanup
2023-01-07 15:42:08 -08:00
David Harris
7f7605737f
Cache code cleanup
2023-01-07 15:39:13 -08:00
David Harris
cdcee61aac
vclean working; started removing unused signals
2023-01-07 05:34:58 -08:00
Ross Thompson
693f32973f
Minor optimizations.
2022-12-23 20:11:36 -06:00
David Harris
93bb8036be
Revert to 98b824
2022-12-22 23:58:14 -08:00
David Harris
567f76c2a5
Code cleanup
2022-12-22 10:04:50 -08:00
Ross Thompson
b3ff4fe02e
CacheEn enables reading or writing the cache memory arrays. This is only disabled if we have a stall while in the ready state and we don't have a cache miss. This is a cache hit, but we are stalled.
2022-12-21 22:13:05 -06:00
Ross Thompson
d1aa5ba890
Updated cache fsm names to match book.
2022-12-21 16:49:53 -06:00
David Harris
c26c3b76ea
Renamed renamed sram to ram
2022-12-20 08:36:45 -08:00
Ross Thompson
c3b77926d5
I think I finally fixed a long hidden bug in the replacement policy. The figures in the textbook are correct. There was small bug in the rtl.
2022-12-18 18:30:35 -06:00
Ross Thompson
5acdf541b9
Finally fixed the lru bug. It was actually a flush bug all along. At the end of flush writeback FlushAdr is incremented so clearly the dirty bit then clears the wrong set. Must either take an additional cycle to clear dirty and then change the address or clear the dirty bit before the cache bus acknowledgment. Changed it to clear at begining of that line's writeback before actually writting back.
2022-12-17 23:47:49 -06:00
Ross Thompson
9849983348
At long last found the subtle bug in the LRU.
...
Since the LRU memory is two ports, 1 read and 1 write, a write in cycle 1 to address x should not
forward data to a read from address y in cycle 2.
A read form address x in cycle 2 would still require forwarding.
2022-12-17 10:03:08 -06:00
Ross Thompson
c985988867
Fixed a bug with the new cache flush changes.
2022-12-16 19:28:32 -06:00
Ross Thompson
5f556817c7
Further cleanfsm cleanup.
2022-12-16 16:37:45 -06:00
Ross Thompson
493b1a4280
More cachefsm cache flush cleanup.
2022-12-16 16:32:21 -06:00
Ross Thompson
3132246a46
Oups found a bug with the new flush cache states.
2022-12-16 16:22:40 -06:00
Ross Thompson
91e64a0d67
Cleanup of cache flush fsm enhancement.
2022-12-16 15:36:53 -06:00
Ross Thompson
ab3c5a0ca7
Rough draft of cache flush fsm enhancement.
2022-12-16 15:28:22 -06:00
Ross Thompson
4a0e4aed99
Signal renames to reflect figures.
2022-12-14 09:49:15 -06:00
Ross Thompson
b69aa39f30
Reduced complexity of linebytemask.
2022-12-14 09:34:29 -06:00
Ross Thompson
6d573b32d2
Changed CPUBusy to Stall in ebu modules.
2022-12-11 15:51:35 -06:00
Ross Thompson
232f866ad1
Renamed CPUBusy to Stall in cache.
2022-12-11 15:49:34 -06:00
Ross Thompson
d3b2e331c2
Added comments about why it is not possible to use FlushWay and VictimWay directly.
2022-12-09 17:07:35 -06:00
Ross Thompson
1a24e7029f
Minor simplification of cacheway way selection muxes.
2022-12-09 16:42:05 -06:00
Ross Thompson
1a9c932157
Renamed SelBusBuffer to SelFetchBuffer.
2022-12-05 17:51:13 -06:00
Ross Thompson
92066f81b6
Removed commented code.
2022-12-05 17:21:56 -06:00
Ross Thompson
37551ecc43
Renamed VictimTag to just Tag. Tag is used for both the victim and flush tags.
2022-12-05 17:19:51 -06:00
Ross Thompson
dc31add951
Cache signal renames.
2022-12-04 16:09:09 -06:00
Ross Thompson
9bf0eedf73
Optimized way selection logic.
2022-12-04 12:30:56 -06:00
Ross Thompson
a130a96b45
Found possible optimization as the way selection is shared in cache, cacheway, and cachelru.
2022-12-04 01:20:51 -06:00
Ross Thompson
3dea04e644
Moved selectedway mux into cacheway. It makes way more sense there.
2022-12-04 01:15:47 -06:00
Ross Thompson
f557150cae
Rename LineByteMux to FetchbufferbyteSel.
2022-12-04 01:00:04 -06:00
