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Author SHA1 Message Date
Ross Thompson
96aa106852 Found bug in the PMA such that invalid addresses were sent to the tim. Once addressing this issue the sv48 test fails early with a pma access fault. 2021-07-15 11:56:35 -05:00
Ross Thompson
4549a9f1c9 Merge branch 'main' into dcache 2021-07-15 11:55:20 -05:00
Ross Thompson
5fb5ac3d5a Updated wave file. 2021-07-15 11:04:49 -05:00
Ross Thompson
c39a228266 Fixed how the dcache and page table walker stall cpu so that once a tlb miss occurs the CPU is always stalled until the walk is complete, the tlb updated, and the dcache fetched and hits. 2021-07-15 11:00:42 -05:00
Ross Thompson
c954fb510b Renamed DCacheStall to LSUStall in hart and hazard. 
Added missing logic in lsu.
 2021-07-15 10:16:16 -05:00
Kip Macsai-Goren
09078ea8ab Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-15 10:52:39 -04:00
Ross Thompson
f234875779 dcache STATE_CPU_BUSY needs to assert CommittedM. This is required to ensure a completed memory operation is not bound to an interrupt. ie. MEPC should not be PCM when committed. 2021-07-14 23:08:07 -05:00
Ross Thompson
6163629204 Finally have the ptw correctly walking through the dcache to update the itlb. 
Still not working fully.
 2021-07-14 22:26:07 -05:00
Katherine Parry
701ea38964 Fixed lint warning 2021-07-14 21:24:48 -04:00
Ross Thompson
d41c9d5ad9 Added d cache StallW checks for any time the cache wants to go to STATE_READY. 2021-07-14 17:25:50 -05:00
Ross Thompson
d3a1a2c90a Fixed d cache not honoring StallW for uncache writes and reads. 2021-07-14 17:23:28 -05:00
Katherine Parry
f8b76082e4 fpu unpacking unit created 2021-07-14 17:56:49 -04:00
Kip Macsai-Goren
723f921f2d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-14 17:30:45 -04:00
Ross Thompson
771c7ff130 Routed CommittedM and PendingInterruptM through the lsu arb. 2021-07-14 16:18:09 -05:00
Ross Thompson
1d7aa27316 Fixed a bug where the dcache did not update the read data if the CPU was stalled, but the memory not stalled. 2021-07-14 15:47:38 -05:00
Ross Thompson
3092e5acdf Forgot to include one hot decoder. 2021-07-14 15:46:52 -05:00
Ross Thompson
e17de4eb11 Separated interruptM into PendingInterruptM and InterruptM. The d cache now takes in both exceptions and PendingInterrupts. 
This solves the committedM issue.
 2021-07-14 15:00:33 -05:00
bbracker
04ce2f7256 testvector unlinker for dev purposes 2021-07-14 11:05:34 -04:00
James Stine
a2c0753edb put back for now to test fdiv 2021-07-14 06:48:29 -05:00
Abe
853e1167a2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-14 04:47:31 -04:00
Abe
a823190ce4 Commented out remaining ehitoa function declaration/calls and related char buff instances. Also commented out extra libraries not currently in use 2021-07-14 04:46:11 -04:00
bbracker
9b6d45ead9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-14 00:21:39 -04:00
bbracker
61e6ebd4d3 make testvector scripts agree with new file structure; use symbols to determine end of linux boot 2021-07-14 00:21:29 -04:00
Ross Thompson
ef598d0e79 Implemented uncached reads. 2021-07-13 23:03:09 -05:00
Ross Thompson
b6e5670bc3 Added CommitedM to data cache output. 2021-07-13 22:43:42 -05:00
bbracker
eb8c1bf5e7 needed to create a directory for gdb script 2021-07-13 19:39:57 -04:00
Ross Thompson
278bbfbe3c Partially working changes to support uncached memory access. Not sure what CommitedM is. 2021-07-13 17:24:59 -05:00
Abe
8d445ef508 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-13 18:22:36 -04:00
Kip Macsai-Goren
f0bf48bbfb Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-13 17:41:47 -04:00
James E. Stine
45a6e96673 mod 2 of fpdivsqrt update 2021-07-13 16:59:17 -04:00
James E. Stine
d695be3ad0 Update fpdivsqrt item until move into uarch 2021-07-13 16:53:20 -04:00
bbracker
2036be2ea4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-13 16:16:04 -04:00
bbracker
dff3970d1c changed QEMU to use different ports 2021-07-13 16:15:51 -04:00
Ross Thompson
b780e471b4 Fixed interaction between icache stall and dcache. On hit dcache needs to enter a cpu busy state when the cpu is stalled. 2021-07-13 14:51:42 -05:00
Ross Thompson
51249a0e04 Fixed the fetch buffer accidental overwrite on eviction. 2021-07-13 14:21:29 -05:00
Ross Thompson
2034a6584f Dcache AHB address generation was wrong. Needed to zero the offset. 2021-07-13 14:19:04 -05:00
Ross Thompson
ee09fa5f58 Moved StoreStall into the hazard unit instead of in the d cache. 2021-07-13 13:20:50 -05:00
David Harris
516b710db6 Fixed busybear by restoring InstrValidW needed by testbench 2021-07-13 14:17:36 -04:00
Ross Thompson
2004b2e044 Fixed back to back store issue. 
Note there is a bug in the lsuarb which needs to arbitrate a few execution stage signals.
 2021-07-13 12:46:20 -05:00
Abe
d71b99383f Downloaded clean version of Coremark from EEMBC github page with which to benchmark RISCV-Wally 2021-07-13 13:37:40 -04:00
David Harris
9af5cef65a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-13 13:26:51 -04:00
David Harris
283c2cda0e added or.sv 2021-07-13 13:26:40 -04:00
Katherine Parry
b9edbb15eb Fixed writting MStatus FS bits 2021-07-13 13:22:04 -04:00
Katherine Parry
acdd2e4504 Fixed writting MStatus FS bits 2021-07-13 13:20:30 -04:00
David Harris
3427d2b7d6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-13 13:19:24 -04:00
David Harris
68d1f87101 Fixed InstrValid from W to M stage for CSR performance counters 2021-07-13 13:19:13 -04:00
bbracker
90eb84cc61 updated buildroot make procedure to incorporate configs more robustly 2021-07-13 12:40:14 -04:00
Ross Thompson
40922cf064 Fixed subword write. subword read should not feed into subword write. 2021-07-13 11:21:44 -05:00
Ross Thompson
a314b3cf68 restored rv64ic config back to full sized dtim. 2021-07-13 11:18:54 -05:00
Ross Thompson
d3ffbe0e5d Modularized the shadow memory to reduce performance hit. 2021-07-13 10:55:57 -05:00