4 Commits

Author	SHA1	Message	Date
David Harris	d9888c91a6	simpleram clk and reset simplification	2022-01-25 17:34:15 +00:00
Ross Thompson	4ecc2d029a	Changed the IROM and DTIM memories to behave like edge-triggered srams.	2022-01-21 15:42:54 -06:00
David Harris	ca1f7ce5d3	Renamed wallypipelinedhart to wallypipelinedcore	2022-01-20 16:02:08 +00:00
Ross Thompson	5726b5b640	Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.	2022-01-13 22:21:43 -06:00