Ross Thompson
d331b9f29d
Fixed "bug" with wally-pipelined.do
2022-02-22 22:19:25 -06:00
bbracker
6caa97bb26
change UART PLIC IRQ mapping from 4 to 10 to match virt model; move WALLY-PERIPH tests to wally arch tests
2022-02-22 03:46:08 +00:00
Ross Thompson
ad237b3ce5
Accidentally cleared dirty bit when setting access bit in hptw.
2022-02-17 16:20:20 -06:00
Ross Thompson
0eec096474
Rough implementation passing regression test with hptw atomic writes to memory.
2022-02-17 14:46:11 -06:00
Ross Thompson
2fc7dc3e57
Fixed a bunch of the virtual memory changes. Now supports atomic update of PTE in memory concurrent with TLB.
2022-02-17 10:04:18 -06:00
Ross Thompson
62f5f1e622
Broken state. address translation not working after changes to hptw to support atomic updates to PT.
2022-02-16 23:37:36 -06:00
Ross Thompson
eafd52e2bc
Added additional suppresses to vsim command incase buildroot files are missing.
2022-02-16 17:05:54 -06:00
Skylar Litz
0c69d3291d
update bugfinder script to new file organization
2022-02-15 22:58:18 +00:00
Ross Thompson
a440bc2ac5
More cache cleanup.
2022-02-13 15:47:27 -06:00
Ross Thompson
1e7e59bdbd
Changed names of signals in cache.
2022-02-13 15:06:18 -06:00
Ross Thompson
b1cba4be2b
Updates to linux wave.
2022-02-11 13:28:18 -06:00
Ross Thompson
9145a96b53
Updated linux wave.
2022-02-11 13:15:42 -06:00
Ross Thompson
3f4ae91468
linux wave cleanup.
2022-02-11 10:48:45 -06:00
Ross Thompson
2f2a4f4500
Fixed subtle and infrequenct bug.
...
Loading buildroot at 483M instructions started with a spill + ITLBMiss. The spillsupport logic allowed transition to the second access only after the bus/cache completed the first operation. However the BusStall was suppressed if ITLBMissF occurs resulting in the spillfsm advancing to the second operation. Now the spill logic also takes in ITLBMissF and prevents the early transition to the second access.
2022-02-11 10:46:06 -06:00
Ross Thompson
9ad4523b9d
Updated wave files to reflect recent changes.
2022-02-10 17:52:19 -06:00
Ross Thompson
327a05c9d8
Added commented out commands to generate saif file from vsim.
2022-02-09 18:40:45 -06:00
David Harris
096242a6d8
Merged TIM and regular testbenches. RV32e now working and back in regression.
2022-02-08 12:18:13 +00:00
David Harris
72c2166223
Lab 3 file cleanup
2022-02-08 10:26:37 +00:00
David Harris
d0c40cca7a
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-02-07 14:43:31 +00:00
David Harris
0feb624bab
Added E tests to wally-riscv-arch-test rv32i_m/I and fixed cyclic path in rv32e configuration
2022-02-06 01:22:40 +00:00
bbracker
fc2e3d1fbf
remove rv32e from regression because it is broken; goes with previous commit
2022-02-05 23:05:21 +00:00
David Harris
0dd8c719ad
Modified regression to use proper rv32e test name, but rv32e_wally32e still isn't passing due to loop exceeding iteration limit
2022-02-05 05:35:51 +00:00
David Harris
f7d6939d9b
Merged buildroot do files into wally-pipelined do files, added work suffixes so buildroot regression won't fail due to file conflicts
2022-02-05 05:28:40 +00:00
David Harris
581fbb7d13
Modified wally-pipelined-batch.do to handle buildroot
2022-02-05 05:07:07 +00:00
David Harris
23868a33bc
Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests.
2022-02-05 04:16:18 +00:00
David Harris
16b5fee795
RV32e tests
2022-02-04 14:30:36 +00:00
David Harris
1c049f1f67
renamed configs
2022-02-03 23:36:41 +00:00
David Harris
e92461159d
cache cleanup
2022-02-03 15:36:11 +00:00
Ross Thompson
4a5aa43716
Merge branch 'makefiles' into main
2022-02-03 08:33:50 -06:00
Ross Thompson
55382be055
Completed makefile updates to accelerate the generation of memfiles. There are two makefiles in the
...
regression directory. Makefile calls the submakefiles for generating elf files.
The second makefile-memfiles generates the memfiles, addr, and label files.
2022-02-03 08:32:48 -06:00
Ross Thompson
9da3223ce6
Manged to get all the tests compiled and converted to memfiles using new makefiles.
2022-02-03 00:00:15 -06:00
Ross Thompson
41978d59e4
Quick patch to regression-wally to "fix" rv32ic.
2022-02-02 19:24:24 -06:00
Ross Thompson
789cf13be6
broken makefiles.
2022-02-02 19:15:11 -06:00
Ross Thompson
ac19cd48a4
Broken makefiles.
2022-02-02 19:14:42 -06:00
David Harris
9e0055cbb9
More config file cleanup; 32ic tests broken
2022-02-03 01:08:34 +00:00
Ross Thompson
f3c2e426b1
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2022-02-02 11:41:54 -06:00
David Harris
761dae72fe
Config file & wally-riscv-arch-test cleanup
2022-02-02 16:35:52 +00:00
Ross Thompson
88a408b3e6
Added helpful signals to wavefile.
...
Makefile for tests now creates the function address to name mapping files.
The function name and test name are included in the wave file.
2022-02-02 10:15:54 -06:00
Ross Thompson
2d8b0aa650
Modified makefiles to generate function address to name mappings for modelsim.
2022-02-01 18:25:03 -06:00
Ross Thompson
058b368a22
Improved function_radix to not printout warnings when no valid function is found.
2022-02-01 18:03:09 -06:00
Ross Thompson
138b17a399
Setup the main regression test to be able to handle coremark.
2022-02-01 17:00:11 -06:00
Ross Thompson
d2ab17e1af
Repaired linux-wave.do
2022-01-31 12:54:18 -06:00
Ross Thompson
3475e142a5
Repaired wavefile and fixed modelsim warning.
2022-01-31 12:34:17 -06:00
Ross Thompson
de0bef4f5b
Updated wave.do to match the ifu/lsu changes.
2022-01-28 14:37:15 -06:00
Ross Thompson
1bb8d36308
Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.
2022-01-27 17:11:27 -06:00
Ross Thompson
d38ab9d2d7
Increased number of concurrent tests.
2022-01-27 08:45:25 -06:00
Ross Thompson
b961b104e0
Added colors to regression script to make it easy to pick out success from fail.
2022-01-26 22:40:32 -06:00
Ross Thompson
23c4ba2777
1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU.
...
2. Removed the write address delay from simpleram.sv
3. Fixed rv32tim and rv32ic mode to handle missalignment correctly.
4. Added imperas32i and imperas32c to rv32tim mode.
2022-01-26 18:23:39 -06:00
David Harris
0bb63e9ad1
Fixed path to riscvOVPsimPlus
2022-01-21 00:12:14 +00:00
David Harris
ca1f7ce5d3
Renamed wallypipelinedhart to wallypipelinedcore
2022-01-20 16:02:08 +00:00
