Ross Thompson
d6960da90e
Moved all bus logic outside the dcache. Still needs cleanup.
2021-12-28 11:18:47 -06:00
Ross Thompson
44b63fc0ba
First cut at moving the dcache bus interface into the LSU.
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Regression test does not run and there is a lot of cleanup to do.
2021-12-27 18:12:59 -06:00
Ross Thompson
3e7ec1e9a2
Moved dcache fetch logic outside the dcache except for the fsm.
2021-12-27 16:45:49 -06:00
Ross Thompson
3ee29785a4
Partial commit.
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Moved AMO, SWW, and SWR outside the dcache.
Step 1 of separate the fetching logic from the caches.
2021-12-27 15:56:18 -06:00
Ross Thompson
50e4463a7f
It was possible for a load/store followed by tlb miss and update to have an exception and still commit its result to memory or register.
2021-12-21 15:59:56 -06:00
Ross Thompson
d830721a11
Fixed Type 5b interaction between dcache and hptw.
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This is a load concurrent with ITLBMiss.
2021-12-20 18:33:31 -06:00
Ross Thompson
6aff6b0fa3
Modified LSU verilog is compatible with vivado. have to use extra logic IEUAdrExtM.
2021-12-20 10:03:56 -06:00
Ross Thompson
53736096a6
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-20 10:03:19 -06:00
Ross Thompson
b261b18aa8
More signal name cleanup in LSU.
2021-12-19 22:47:48 -06:00
Ross Thompson
533c2f3556
Remove verbosity from lsu state machine.
2021-12-19 22:41:34 -06:00
Ross Thompson
82dd41a0fd
Rename of SelPTW to SelHPTW.
2021-12-19 22:24:07 -06:00
Ross Thompson
9c2fc30507
Signal renames.
2021-12-19 22:21:03 -06:00
Ross Thompson
2f5de7eb82
Hardware reductions in the lsu.
2021-12-19 22:00:28 -06:00
Ross Thompson
30770db4ac
Removed lsuArb and placed remaining logic in lsu.sv.
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Removed after itlb walk signal as the dcache no longer has any need for this.
Formated lsu.sv
2021-12-19 21:34:40 -06:00
Ross Thompson
cef4b6399d
Switched to using an always block for lsu stall logic. This avoids the problematic x propagation.
2021-12-19 18:16:08 -06:00
Ross Thompson
814bcec7b7
Implemented what I think is the last required change for the lsu state machine.
2021-12-19 17:57:12 -06:00
Ross Thompson
54fd8678b0
Created hack to get around imperas64mmu unknown (value = x) bug.
2021-12-19 17:53:13 -06:00
Ross Thompson
04d0b85f96
Fixed bug most of the bugs related to the dcache changes, but the mmu tests don't pass.
2021-12-19 16:12:31 -06:00
Ross Thompson
202203904c
Corrected the LSU's fsm for stalling CPU. Removed state from hptw fsm.
2021-12-19 15:10:33 -06:00
Ross Thompson
9adcf86a40
Modified the icache memory to read using the virtual (non physical) address in the PCNextF stage.
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This allows recovering from an ITLBMiss to be 1 cycle after and simplifies the hptw slightly.
2021-12-19 14:57:42 -06:00
Ross Thompson
0257c08641
Renamed MemAdrM to IEUAdrM. This will free the name MemAdrm for use in the DCache.
2021-12-19 14:00:30 -06:00
Ross Thompson
620f4a58d4
Adds FSM to LSU which will handle the interactions between the hptw and dcache. This will dramatically simplify the dcache by removing all walker states.
2021-12-19 13:55:57 -06:00
Ross Thompson
f601b3ae53
Merge branch 'tlb_fixes' into main
2021-12-18 12:24:17 -06:00
Ross Thompson
2f86e84843
Merge remote-tracking branch 'origin/tlb_fixes' into main
2021-12-17 14:40:29 -06:00
Ross Thompson
79ec4161b6
Added more debugging code for FPGA.
2021-12-17 14:40:25 -06:00
Ross Thompson
5264577dcf
Possible fix for icache deadlock interaction with hptw.
2021-12-17 14:38:25 -06:00
David Harris
3a9071e509
Renamed MemAdrE to IEUAdrE and moved the MemAdrM flop from IEU to LSU to reduce wires crossing hierarchies
2021-12-15 12:10:45 -08:00
David Harris
f4957fdac1
Renamed dtim->ram and boottim ->bootrom
2021-12-14 13:43:06 -08:00
Ross Thompson
45b38ea9fe
Comments for dcache and icache refactoring.
2021-12-14 14:46:29 -06:00
slmnemo
acacd13ffc
Removed .* from mmu instance inside lsu.sv.
2021-12-08 00:15:30 -08:00
Ross Thompson
2f85ac7f38
Fixed a very complex interaction between interrupts, the icache, dcache, and hptw.
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If an interrupt occurred at the start of an ITLB miss or DTLB miss the page table
walk should be aborted before starting.
2021-11-20 22:35:47 -06:00
Ross Thompson
87aaec3b6c
Partial cleanup of unused signals in caches and bpred.
2021-10-24 15:04:20 -05:00
David Harris
106982e493
more lsu/ifu lint cleanup
2021-10-23 12:10:13 -07:00
David Harris
8b1dc81d34
more lsu/ifu lint cleanup
2021-10-23 12:00:32 -07:00
David Harris
88b2d9e687
lsu/ifu lint cleanup
2021-10-23 11:41:20 -07:00
David Harris
708b914a65
Lint cleanup from wallypipeliendhart
2021-10-23 10:29:52 -07:00
Ross Thompson
99d675b872
Finished adding the d cache flush. Required ensuring the write data, address, and size are
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correct when transmitting to AHBLite interface.
2021-09-17 13:03:04 -05:00
Ross Thompson
d4398c23fb
Added states and all control and data path logic to support d cache flush. This is currently untested; however the existing regresss test passes.
2021-09-16 18:32:29 -05:00
David Harris
72c1cc33f5
Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.
2021-09-15 13:14:00 -04:00
Ross Thompson
bf312bb37c
Removed amo logic from ahblite. Removed many unused signals from ahblite.
2021-08-25 22:45:13 -05:00
Ross Thompson
05a32508eb
Dcache and LSU clean up.
2021-08-10 13:36:21 -05:00
Ross Thompson
0291d987da
Added additional interlock for itlb miss -> instrPageFault with concurrent memory operation.
2021-07-25 23:14:28 -05:00
Ross Thompson
32ec457e09
Removed the hardware page table walker fault state from the icache so that the icache will only unstall CPU for 1 cycle.
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In the dcache we added a register to save the load read data in the event an itlb miss occurs concurrently with
the load in the memory stage. Under this situation we need to record the load ReadDataM into a temporary register,
SavedReadDataM. At this time the CPU is stall; however the walker is going to change the address in the dcache
which destroys this data. When leaving the PTW_READY state via a walker instruction fault or ITLB write we select
this SavedReadDataM so that the CPU can capture it.
2021-07-22 19:42:19 -05:00
Ross Thompson
007812dbdc
Moved the ReadDataW register into the datapath.
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The StallW from the hazard unit controls this.
Previously it was in the dcache and controlled by both the HPTW and hazard unit.
This caused an issue when the CPU expected the data to stay constant while
stalled, but the HPTW was causing the data to be modified.
2021-07-22 14:52:03 -05:00
Ross Thompson
936e034be9
Fixed bug with the itlb fault not dcache ptw ready state to ready state.
2021-07-22 14:04:56 -05:00
Ross Thompson
511c36fb1b
Improved address bus names and usages in the walker, dcache, and tlbs.
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Merge branch 'walkerEnhance' into main
2021-07-21 14:55:09 -05:00
Ross Thompson
ae2371f2ce
Added performance counters for dcache access and dcache miss.
2021-07-19 22:12:20 -05:00
Ross Thompson
6ccbdc372d
Broken.
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Possible change to walker, dcache, tlb addressing.
Improves the naming of address signals.
But has a problem when the walker finishes the dcache does not get the correct
address on the cycle the DTLB is updated. This leads to incorrect index
selection in the dcache.
2021-07-19 10:33:27 -05:00
David Harris
e31d2ef9f5
Renamed pagetablewalker to hptw
2021-07-18 04:11:33 -04:00
Ross Thompson
d0ed6e250a
Fixed LRSC in 64bit version. 32bit version is broken.
2021-07-17 20:58:49 -05:00
