69 Commits

Author	SHA1	Message	Date
David Harris	23868a33bc	Temporarily changed rv32e config to use TIM, but it still fails. Added rv32e tests.	2022-02-05 04:16:18 +00:00
David Harris	14c1d86953	rv32e	2022-02-04 01:56:30 +00:00
David Harris	1c049f1f67	renamed configs	2022-02-03 23:36:41 +00:00
David Harris	9e0055cbb9	More config file cleanup; 32ic tests broken	2022-02-03 01:08:34 +00:00
David Harris	bdf1a8ba73	changed DMEM and IMEM configurations to support BUS/TIM/CACHE	2022-02-03 00:41:09 +00:00
David Harris	172a02551b	Removed Busybear and Buildroot Configuration	2022-02-02 20:32:22 +00:00
David Harris	761dae72fe	Config file & wally-riscv-arch-test cleanup	2022-02-02 16:35:52 +00:00
David Harris	2d112698b7	Replaced || and && with | and &	2022-01-31 01:07:35 +00:00
David Harris	975c0e72c8	Set up rv32emc config	2022-01-27 14:37:58 +00:00
David Harris	c6adb7b6b1	Updated configs to fix GPIO address to match FU540	2022-01-26 18:16:34 +00:00
David Harris	5842d780a7	Defined rv32e and rv32emc configs	2022-01-17 14:01:01 +00:00
Ross Thompson	ce937a35a8	Added tim only test to regression-wally. Minor cleanup to ifu.	2022-01-14 11:13:06 -06:00
Ross Thompson	5726b5b640	Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.	2022-01-13 22:21:43 -06:00
Ross Thompson	9f7e3f147b	Partial local dtim in lsu configuration.	2022-01-13 17:50:31 -06:00
Ross Thompson	ecd3912900	Set rv32ic to not use icache.	2022-01-12 14:10:09 -06:00
David Harris	50c17f2a03	Removed unused coremark_bare	2022-01-10 05:05:55 +00:00
David Harris	467aac8463	Added riscvsingle. Removed unnecessary coremark config. Added compiler flags for Coremark.	2022-01-10 05:04:13 +00:00
Ross Thompson	888a60d8d6	Switched block for line in caches.	2022-01-04 22:08:18 -06:00
David Harris	115287adc8	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00