244 Commits

Author	SHA1	Message	Date
David Harris	d1839b6db2	Remove conditional from inside decompress module	2023-01-07 05:51:47 -08:00
David Harris	0a011f4548	Remove unused signals	2023-01-07 05:46:22 -08:00
Ross Thompson	34f8f2c47a	Added more missing files.	2023-01-06 00:12:08 -06:00
Ross Thompson	0081ff92f9	Addd missing file.	2023-01-06 00:09:18 -06:00
Ross Thompson	e34f80db2f	More branch predictor cleanup.	2023-01-05 17:19:27 -06:00
Ross Thompson	010168a69e	Keep around the old gshare.	2023-01-05 15:55:46 -06:00
Ross Thompson	f3d871f2c3	Added speculative gshare.	2023-01-05 14:18:00 -06:00
Ross Thompson	3637067ace	Officially added global history with speculation to types of branch predictors.	2023-01-05 14:04:09 -06:00
Ross Thompson	8ca6c1255e	More branch predictor cleanup.	2023-01-05 13:36:51 -06:00
Ross Thompson	bca87d326b	Two bit predictor cleanup.	2023-01-05 13:27:22 -06:00
Ross Thompson	87c9682311	Simplified gshare.	2023-01-04 23:51:09 -06:00
Ross Thompson	f8c656f1e0	Simiplified global history branch predictor.	2023-01-04 23:41:55 -06:00
davidharrishmc	f1c950a5a7	Update decompress.sv ... typo	2023-01-04 17:01:26 -08:00
Ross Thompson	5d844801d2	Fixed problems with changes to ram2p.	2022-12-29 17:13:48 -06:00
Ross Thompson	1f42098758	Added about moving decompressed config generate.	2022-12-27 15:04:55 -06:00
Ross Thompson	1d11ff6153	Added missing assignment for no branch predictor mode.	2022-12-24 17:08:29 -06:00
Ross Thompson	b5a85b55f1	Reverted to naming IFUStallD to IFUStallF and LSUStallW to LSUStallM. These are generated in the F and M stage. ... Generate WFIStallM in the privileged unit rather than generate in hazard. Cleaned up the hazard cause logic to be consistent across all causes.	2022-12-23 15:10:37 -06:00
Ross Thompson	6b105bd217	Renamed IFU and LSU stalls.	2022-12-22 21:56:33 -06:00
Ross Thompson	ce7e1073fa	Success we've replaced TrapM with FlushD in the IFU.	2022-12-22 21:36:49 -06:00
Ross Thompson	677f6f8737	Partial cleanup for BP.	2022-12-22 20:33:38 -06:00
Ross Thompson	942acb354e	Closing in on icache flushed by FlushD rather than TrapM.	2022-12-22 20:19:09 -06:00
Ross Thompson	47d61984ad	First pass at resolving ifu flush on trap rather than FlushD.	2022-12-22 15:53:06 -06:00
Ross Thompson	0cb2cf9a5b	Changed GatedStallF to GatedStallD.	2022-12-21 16:12:55 -06:00
Ross Thompson	2b1e9f8bed	The optimzied PC+2/4 logic still hanges on wally32priv.	2022-12-21 09:19:34 -06:00
Ross Thompson	a2329c8e9d	Renamed PCPlusUpperF to PCPlus4F.	2022-12-21 09:18:30 -06:00
Ross Thompson	3fc121ef70	Fixed minor bug in PLIC. reading interrupt source 0 should not return x. it should provide produce 0. ... Switched to even simplier PC+2/4 logic.	2022-12-21 09:00:09 -06:00
Ross Thompson	bc5d5e902a	Comments about PC+2/4.	2022-12-21 08:35:43 -06:00
Ross Thompson	6152c028db	Merge branch 'main' of github.com:davidharrishmc/riscv-wally	2022-12-20 18:09:37 -06:00
Ross Thompson	cba2ed64e5	Moved privileged pc logic into privileged unit.	2022-12-20 17:55:45 -06:00
David Harris	07dc11a508	IFU mux for CSRWriteFenceM conditional on ZICSR/ZIFENCEI	2022-12-20 15:38:30 -08:00
Ross Thompson	b4bdf446cc	Implement FENCE.I as NOP when ZIFENCEI is not supported.	2022-12-20 17:34:11 -06:00
David Harris	f03d4e6b5a	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-12-20 14:43:33 -08:00
David Harris	9133b3a7a4	FPU remove unused signals	2022-12-20 14:43:30 -08:00
Ross Thompson	637df763ca	Renumbered bits for PCPlusUpper.	2022-12-20 16:33:49 -06:00
Ross Thompson	ca6076445b	Merge branch 'main' of github.com:davidharrishmc/riscv-wally	2022-12-20 12:58:59 -06:00
Ross Thompson	d35fc5e2a6	Reorganized IFU PCNextF logic.	2022-12-20 12:58:54 -06:00
David Harris	c26c3b76ea	Renamed renamed sram to ram	2022-12-20 08:36:45 -08:00
David Harris	b575f6242e	Renamed SRAM2P1R1W to lower case	2022-12-20 02:09:36 -08:00
Ross Thompson	67e0b021ae	several options for pcnextf on fence.i	2022-12-19 23:33:12 -06:00
Ross Thompson	d18ef45c18	More bp/ifu pcmux cleanup.	2022-12-19 23:16:58 -06:00
Ross Thompson	761cf54dcc	Moved more muxes inside bp.	2022-12-19 22:51:55 -06:00
Ross Thompson	0097c166d6	Begin cleanup of ifu. partial move of pc muxes inside bp.	2022-12-19 22:46:11 -06:00
David Harris	2393915bf2	Simplified InstrRawD register	2022-12-19 15:18:42 -08:00
Ross Thompson	c253b882be	Reworked the hazards to eliminate StallFCause. Flush and CSRWrites now flush F,D,E stages and set the correct PCNextF in the M stage.	2022-12-15 09:53:35 -06:00
Ross Thompson	dbc3dac03d	Removed unused flushf.	2022-12-11 16:28:11 -06:00
Ross Thompson	ad7dd56180	Renamed CPUBusy to GatedStallF in IFU.	2022-12-11 15:54:19 -06:00
Ross Thompson	6d573b32d2	Changed CPUBusy to Stall in ebu modules.	2022-12-11 15:51:35 -06:00
Ross Thompson	232f866ad1	Renamed CPUBusy to Stall in cache.	2022-12-11 15:49:34 -06:00
Ross Thompson	f09b9e1572	Finished merge of kip and ross's ifu fix.	2022-12-09 16:52:22 -06:00
Ross Thompson	981ac3963a	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-12-09 16:42:16 -06:00