Katherine Parry
d0e708f239
FMA uses one LOA
2021-12-07 14:15:43 -08:00
bbracker
d459e35645
undo intentionally breaking commit
2021-12-07 13:43:47 -08:00
bbracker
3379b74bb2
intentionally breaking commit
2021-12-07 13:27:34 -08:00
bbracker
cf61187273
undo intentionally breaking commit
2021-12-07 13:27:06 -08:00
bbracker
69f025a642
intentionally breaking commit
2021-12-07 13:23:19 -08:00
bbracker
ec6c3bd74c
2nd attempt at making regression-wally.py able to be run from a different dir
2021-12-07 13:13:30 -08:00
bbracker
0c48725fa5
fix checkpointing so that it can find the synchronized reset signal
2021-12-07 13:12:06 -08:00
bbracker
9fc4f3bfef
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-07 11:16:51 -08:00
bbracker
0692372037
attempt to make regression-wally.py more path-independent such that git bisect can invoke it directly
2021-12-07 11:16:43 -08:00
Ross Thompson
51e2b9ea6f
Added information on how to copy the linux image to flash card.
2021-12-07 13:16:38 -06:00
bbracker
8e2a9d5bbb
add buildroot tv linking to make-tests.sh
2021-12-07 11:15:59 -08:00
Ross Thompson
c7be8a701e
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-12-07 13:12:59 -06:00
Ross Thompson
8bb3d51aad
Added generate around the dtim preload.
...
Added readme to explain FPGA.
2021-12-07 13:12:47 -06:00
Ross Thompson
3d829dbbd3
Fixed two issues.
...
First the xci files already include the xdc constraints for each IP block. There is no need to include the xdc files explicitly.
Second the bidir buffer for the sd card was connected backwards.
2021-12-07 12:15:50 -06:00
bbracker
ffe7cf83e5
regression.py bugfix
2021-12-06 19:32:38 -08:00
bbracker
b714490f92
add make-tests scripts
2021-12-06 15:37:33 -08:00
bbracker
d702599d56
add buildroot-only option to regression
2021-12-06 14:13:58 -08:00
bbracker
6c9db52801
linux-testvectors symlinks shouldn't be in repo, especially not in this location
2021-12-05 22:03:51 -08:00
Ross Thompson
517cae796c
Fixed more constraint issues in fpga.
...
Added back in the ILA.
Design does not work yet. Stil having issues with order of automatic
clock and I/O constraint ordering.
Added back in the preload for the boottim.
2021-12-05 15:14:18 -06:00
David Harris
19fb0aace8
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-12-04 20:26:01 -08:00
David Harris
83765ea3bc
Added files to repo
2021-12-04 20:25:33 -08:00
Skylar Litz
a69ab3bd1b
fix some interrupt timing bugs
2021-12-03 12:32:38 -08:00
Ross Thompson
755c3e6a4c
Fixed buildroot to work with the fpga's merge.
2021-12-02 18:09:43 -06:00
Ross Thompson
74ffb48c0a
Mostly integrated FPGA flow into main branch. Not all tests passing yet.
2021-12-02 18:00:32 -06:00
Ross Thompson
b7e8c74e61
Merge branch 'fpga' into main
2021-12-02 14:28:10 -06:00
kwan
e4f214090d
.* resolved in ifu.sv
2021-12-02 10:32:35 -08:00
kwan
2a77bc8053
.* in ifu/ifu.sv eliminated
2021-12-02 09:45:55 -08:00
David Harris
e4861e11d1
Added coremark scripts to regression directory
2021-12-01 09:08:06 -08:00
David Harris
273e211660
testing push
2021-11-30 11:20:09 -08:00
Ross Thompson
d7df9c1054
Fixed uart for FPGA config after merge. This still needs some work.
2021-11-29 16:07:54 -06:00
Ross Thompson
8e4eacc18e
Merge branch 'main' into fpga
2021-11-29 10:10:37 -06:00
Ross Thompson
e43aa6ead4
Merge branch 'main' into fpga
2021-11-29 10:06:53 -06:00
bbracker
c5d393fbc6
UART hack now looks at physical addresses so that it isn't bamboozled by S-mode accesses
2021-11-25 11:01:59 -08:00
Noah Limpert
cb77c1db3a
updated fpu instantion on wallypiplinedhart to remove .*, updated spacing as well
2021-11-24 23:22:04 -08:00
Noah Limpert
e66fdd3f80
replaced .* instation of priv module on wallypiplinedhart
2021-11-24 22:58:59 -08:00
Noah Limpert
0cd31bfc1f
Made abhlite instation on wallypipehart more clear, updated spacing for consistency
2021-11-24 22:48:01 -08:00
Noah Limpert
8a64510ee4
updated module instation of LSU on wallypiplinedhard
2021-11-24 22:09:39 -08:00
bbracker
de8e2008d2
fix parseState.py to correctly take in PMPCFG
2021-11-24 16:52:51 -08:00
Ross Thompson
b909375289
Missed another change to uart.
2021-11-23 10:20:47 -06:00
Ross Thompson
fe00729d7c
Fixed syntax error which modelsim did not detect in my changes for making uart work with qemu's simulation.
2021-11-23 10:00:32 -06:00
Ross Thompson
e309017ec4
Added QEMU hack for initial LCR value in uart.
2021-11-22 15:23:19 -06:00
Ross Thompson
e568068c78
Hack added to uart so QEMU simulation can work with an ultra fast baud rate relative to the clock speed.
2021-11-22 15:20:54 -06:00
Ross Thompson
fcd14828d4
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-11-22 11:30:14 -06:00
bbracker
d90d708cf9
activate STVAL for buildroot
2021-11-21 10:40:28 -08:00
Ross Thompson
c661bb4894
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-11-20 22:44:45 -06:00
Ross Thompson
d080041508
Removed unneeded check for icache ways.
2021-11-20 22:44:37 -06:00
Ross Thompson
baa98e7015
Reversed bit order in uart.
2021-11-20 22:43:05 -06:00
Ross Thompson
4443fca5c5
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-11-20 22:37:15 -06:00
Ross Thompson
2f85ac7f38
Fixed a very complex interaction between interrupts, the icache, dcache, and hptw.
...
If an interrupt occurred at the start of an ITLB miss or DTLB miss the page table
walk should be aborted before starting.
2021-11-20 22:35:47 -06:00
bbracker
9e4033935f
add checkpoints to regression
2021-11-20 19:42:53 -08:00
