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Author	SHA1	Message	Date
David Harris	b614f165fb	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-08-01 15:47:58 -07:00
David Harris	91597bba87	lza cleanup	2022-08-01 15:47:03 -07:00
David Harris	f56b26ec40	lza cleanup	2022-08-01 15:43:48 -07:00
David Harris	c3e9719c99	lza cleanup	2022-08-01 15:40:12 -07:00
David Harris	d6b5e7a6ef	lza cleanup	2022-08-01 15:37:09 -07:00
Katherine Parry	8ff3a693af	regression passes fpu tests	2022-08-01 19:56:25 +00:00
Katherine Parry	9c68f85822	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-08-01 19:55:50 +00:00
David Harris	2869d67e50	more lza cleanup	2022-08-01 12:34:00 -07:00
David Harris	b34d2065c3	LZA cleanup	2022-08-01 12:30:42 -07:00
David Harris	99462049e7	LZA refactoring switched to Pp1, Gm1, Km1	2022-08-01 12:20:23 -07:00
David Harris	3c08aabcd3	LZA refactoring	2022-08-01 11:36:21 -07:00
Katherine Parry	eddf6e9ee1	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-08-01 18:35:07 +00:00
David Harris	7f9b601467	fmalza edits to match textbook	2022-08-01 18:23:39 +00:00
David Harris	257107f908	Partitioned fma into separate files	2022-08-01 18:07:38 +00:00
Ross Thompson	1ee613ae6c	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-07-31 12:48:51 -05:00
Katherine Parry	1bd6351e1f	re-added FStore2 in Cache	2022-07-29 22:54:49 +00:00
David Harris	93d7d7179e	Added parity and stop bit tests to UART	2022-07-28 04:35:51 +00:00
David Harris	429bdae1c4	Fixed UART reference output	2022-07-27 22:16:38 +00:00
David Harris	b08c87cb47	Finished UART test	2022-07-27 04:06:59 +00:00
David Harris	75a265159b	Increased timeout threshold to avoid timeout building riscof tests on slow machine	2022-07-27 04:05:21 +00:00
slmnemo	7348af7fd5	Updated reference file for UART test	2022-07-26 09:39:31 -07:00
slmnemo	a9d5805990	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-07-26 09:15:20 -07:00
slmnemo	5218865a7f	Committing changes made to UART test	2022-07-26 09:14:40 -07:00
David Harris	9ecef0c4cd	fixed testbench merge comflict	2022-07-26 06:21:46 -07:00
David Harris	2d7f4b133c	More work toward riscof tests	2022-07-26 06:19:13 -07:00
David Harris	766252db1b	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-25 23:29:08 +00:00
David Harris	5c54c5b521	Added rv32f tests to RV64gc	2022-07-25 23:29:05 +00:00
David Harris	c6a58eb5b6	Tests making successfully except for rv32gc_arch32f, which has FLEN=64 and tries using fld/fsd	2022-07-25 16:23:10 -07:00
David Harris	416f5edfe0	More riscof makefile tuning	2022-07-25 21:15:56 +00:00
David Harris	7f7b3359b0	Cleaning up Makefiles for riscof to run each set of tests individually and eliminate warnings	2022-07-25 20:50:38 +00:00
David Harris	62be9963d8	Fixed synthesis by removing wally-config.vh at level above hdl directory	2022-07-25 01:50:38 +00:00
Ross Thompson	40e7cda84a	Don't use this commit yet. Untested.	2022-07-24 15:40:52 -05:00
Ross Thompson	719b00e338	Overlapped read fetch line end with eviction write line start. I'm a bit concerned this is not well tested.	2022-07-24 01:20:29 -05:00
Ross Thompson	69d520a7eb	Removed replay from the config files.	2022-07-24 00:34:11 -05:00
Ross Thompson	f3cf46d633	Added more i-cache signals to wave file.	2022-07-24 00:24:13 -05:00
Ross Thompson	cd68896637	Merged evict dirty clear with flush write back.	2022-07-24 00:22:43 -05:00
Ross Thompson	8193946996	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-07-23 08:41:59 -05:00
Ross Thompson	05484c4c05	signal name cleanup.	2022-07-22 23:36:27 -05:00
Ross Thompson	27e32980ad	cache cleanup after removing replay on cpubusy.	2022-07-22 23:30:25 -05:00
Ross Thompson	17ae1a1b1b	cache fsm cleanup after removal of replay.	2022-07-22 23:25:09 -05:00
Ross Thompson	abc79c6c8e	Possible improvement to cache which removes the cpu_busy states.	2022-07-22 23:20:37 -05:00
Katherine Parry	655e2d3810	merged radix-2 sqrt into divider - doesnt work yet	2022-07-23 00:41:18 +00:00
slmnemo	bfced6bfe8	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-07-22 17:13:38 -07:00
slmnemo	ca4511b6dc	Fixed UART FIFO bugs and added FIFO tests	2022-07-22 17:13:19 -07:00
Daniel Torres	d0aaae26fe	fixed wally rv32e tests, updated regression makefile to new testflow	2022-07-22 17:09:46 -07:00
Daniel Torres	35878755f5	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-07-22 15:35:25 -07:00
Daniel Torres	4da96c5791	fixed 32priv tests, now passing	2022-07-22 15:35:20 -07:00
Katherine Parry	b3d932cd61	divider sizes reworked to match book	2022-07-22 22:02:04 +00:00
Daniel Torres	24828db612	changes to test.vh for compatability	2022-07-22 15:00:48 -07:00
Daniel Torres	4198145ce2	added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail	2022-07-22 14:58:55 -07:00