28 Commits

Author	SHA1	Message	Date
David Harris	62e6aed7e5	Simplified performance counters	2021-12-31 06:40:21 +00:00
David Harris	5d4014d351	Refactoring ALU and datapath muxes	2021-12-08 12:33:53 -08:00
Ross Thompson	e43aa6ead4	Merge branch 'main' into fpga	2021-11-29 10:06:53 -06:00
Ross Thompson	b8572d6a2a	Changed several things. ... Removed the need to use async flip flops in SDC. Added arrs, a synchronizer for reset. I think this works with the real FPGA hardware. The last build did not include this arrs but it worked.	2021-11-12 11:13:50 -06:00
Ross Thompson	2f4ee26b60	Fixed issue with dtim (fpga) external abhlite select not triggering. ... Setup the bootloader (bios.s) to copy 127MB and blink LEDs for 5 seconds with 1 second period.	2021-10-25 14:51:54 -05:00
Ross Thompson	f7583d0e0d	Updated uncore to use sdc. ... Fixed bug with fence instruction not correctly clearing dirty bits in d cache.	2021-10-25 14:07:44 -05:00
David Harris	47124f36c8	Added synchronizer to reset	2021-10-25 10:05:41 -07:00
David Harris	5e961973cb	IEU lint cleanup	2021-10-23 10:51:53 -07:00
David Harris	708b914a65	Lint cleanup from wallypipeliendhart	2021-10-23 10:29:52 -07:00
Ross Thompson	09dc3e1143	Merge branch 'main' into fpga	2021-10-20 16:24:55 -05:00
David Harris	687703f0d8	removed .* from wallypipeliendsoc	2021-10-20 13:49:18 -07:00
Ross Thompson	db18aac9af	Partially sd card read on fpga.	2021-09-30 11:23:09 -05:00
Ross Thompson	55f3c15302	Merge branch 'sdc' into fpga	2021-09-25 19:33:07 -05:00
Ross Thompson	4256ef82b1	SDC to ABHLite interface partially done. ... Added SDC to adrdec and uncore.	2021-09-24 10:45:09 -05:00
Ross Thompson	b04e00d196	Third attempt at fixing the write enables for the icache cacheway.	2021-09-09 15:49:27 -05:00
David Harris	1972d83002	Refactored pmachecker to have adrdecs used in uncore	2021-06-23 01:41:00 -04:00
bbracker	b43a8885cd	give EBU a dedicated PMA unit as just an address decoder	2021-06-22 18:28:08 -04:00
David Harris	e03912f64c	Cleaned up name of MTIME register in CSRC	2021-06-18 07:53:49 -04:00
bbracker	7d1469a06c	provide time and timeh CSRs based on CLINT's counter	2021-06-17 08:38:30 -04:00
Thomas Fleming	e7822ce20c	Implement first pass at the PMA checker	2021-04-22 15:34:02 -04:00
Thomas Fleming	d281ecd067	Remove imem from testbenches	2021-04-14 20:20:34 -04:00
bbracker	ce7b2314ef	Yee hoo first draft of PLIC plus self-checking tests	2021-04-04 06:40:53 -04:00
David Harris	0258901865	Cleaned out unused signals	2021-02-26 09:17:36 -05:00
David Harris	38b8cc652c	All tests passing with bus interface	2021-02-24 07:25:03 -05:00
David Harris	33110ed636	Data memory bus integration	2021-02-07 23:21:55 -05:00
David Harris	616830a3f0	Cleaned up hazard interface	2021-02-02 13:53:13 -05:00
David Harris	92bf1674b4	Moved fpu to temporary location to fix compile and cleaned up interface formatting	2021-02-01 23:44:41 -05:00
David Harris	07af481b67	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00