bbracker
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cd469035be
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make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset
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2021-07-19 15:13:03 -04:00 |
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David Harris
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a67292b5f3
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trap.sv comment cleanup
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2021-07-17 16:01:07 -04:00 |
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David Harris
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c1c3249709
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trap.sv cleanup
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2021-07-17 15:57:10 -04:00 |
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David Harris
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e182cac9bc
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hptw: Removed NonBusTrapM from LSU
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2021-07-17 15:24:26 -04:00 |
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David Harris
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2f81e4c70d
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hptw: Removed NonBusTrapM from LSU
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2021-07-17 15:22:24 -04:00 |
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Ross Thompson
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fa26aec588
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Merge branch 'main' into dcache
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2021-07-15 11:55:20 -05:00 |
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Ross Thompson
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f4295ff097
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Separated interruptM into PendingInterruptM and InterruptM. The d cache now takes in both exceptions and PendingInterrupts.
This solves the committedM issue.
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2021-07-14 15:00:33 -05:00 |
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Katherine Parry
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ca19b2e215
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Fixed writting MStatus FS bits
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2021-07-13 13:22:04 -04:00 |
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Katherine Parry
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efdec72df1
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Fixed writting MStatus FS bits
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2021-07-13 13:20:30 -04:00 |
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David Harris
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b5dddec858
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Fixed InstrValid from W to M stage for CSR performance counters
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2021-07-13 13:19:13 -04:00 |
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David Harris
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5c2f774c35
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Simplified tlbmixer mux to and-or
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2021-07-08 23:34:24 -04:00 |
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David Harris
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74b6d13195
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Fixed missing stall in InstrRet counter
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2021-07-08 20:08:04 -04:00 |
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David Harris
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032c38b7e7
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MMU produces page fault when upper bits aren't equal. Renamed input to MMU to be 'Address' and moved translation mux into MMU out of TLB
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2021-07-06 15:29:42 -04:00 |
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Ross Thompson
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412691df2d
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-07-06 13:45:20 -05:00 |
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Ross Thompson
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3345ed7ff4
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Merged several of the load/store/instruction access faults inside the mmu.
Still need to figure out what is wrong with the generation of load page fault when dtlb hit.
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2021-07-06 13:43:53 -05:00 |
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Abe
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8854532a79
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Disabled MCOUNTINHIBIT to enable csr counters (changed to 32'h0 on line 140)
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2021-07-06 12:37:58 -04:00 |
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David Harris
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f805aea236
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Implemented TSR, TW, TVM, MXR status bits
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2021-07-06 01:32:05 -04:00 |
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David Harris
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8b23162d6d
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Fixed adrdecs to use Access signals for TIMs
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2021-07-05 23:42:58 -04:00 |
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David Harris
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6bac566bb7
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Added support for TVM flag in CSRS and to disabl TLB when MEM_VIRTMEM = 0
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2021-07-05 20:35:31 -04:00 |
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David Harris
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b23192cf1b
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Gave names to for loops in generate blocks for ease of reference
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2021-07-04 18:52:16 -04:00 |
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David Harris
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7e22ae973e
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Fixed MPRV and MXR checks in TLB
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2021-07-04 13:20:29 -04:00 |
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David Harris
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67e191c6f3
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Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries
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2021-07-04 11:39:59 -04:00 |
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David Harris
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0bd18ff662
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Fixed PMPCFG read faults
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2021-07-02 17:08:13 -04:00 |
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David Harris
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c85e0df1ff
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Optimized PMP checker logic and added support for configurable number of PMP registers
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2021-07-02 11:04:13 -04:00 |
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bbracker
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2155a4e485
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Revert "fixed forwarding"
This reverts commit 86e369df52.
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2021-06-24 17:39:37 -04:00 |
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bbracker
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86e369df52
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fixed forwarding
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2021-06-24 11:20:21 -04:00 |
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David Harris
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1ec90a5e1f
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Reversed [0:...] with [...:0] in bus widths across the project
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2021-06-21 01:17:08 -04:00 |
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David Harris
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d2ec04564b
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Cleaned up fcsr code and added _SUPPORTED to optionally disable peripherals
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2021-06-20 22:59:04 -04:00 |
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bbracker
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23f479d225
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remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR
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2021-06-20 22:38:25 -04:00 |
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bbracker
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83a0a37f8e
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make xCOUNTEREN what buildroot expects it to be
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2021-06-20 09:22:31 -04:00 |
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David Harris
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336936cc39
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Cleaned up name of MTIME register in CSRC
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2021-06-18 07:53:49 -04:00 |
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bbracker
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2bee4eabab
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added MTIME and MTIMECMP as read-only CSRs; this likely is not the final version
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2021-06-17 12:09:10 -04:00 |
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bbracker
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b65adbea63
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enable TIME CSR for 32 bit mode as well
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2021-06-17 11:34:16 -04:00 |
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bbracker
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5a661a7392
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provide time and timeh CSRs based on CLINT's counter
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2021-06-17 08:38:30 -04:00 |
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bbracker
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9bc5ddf5f2
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PMPADDRreg size bugfix; PMPADDR_ARRAY_REGW[15] is now useable
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2021-06-17 05:19:36 -04:00 |
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bbracker
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7b98e7aa2f
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mcause test fixes and s-mode interrupt bugfix
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2021-06-16 17:37:08 -04:00 |
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David Harris
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49b5fa3994
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Reverted MIDELEG and MEDELEG to XLEN so busybear passes
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2021-06-10 23:47:32 -04:00 |
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David Harris
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e41a87be23
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Restored counter events
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2021-06-10 11:18:58 -04:00 |
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David Harris
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3e8026dc21
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Configurable number of performance counters
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2021-06-10 09:41:26 -04:00 |
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David Harris
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01d6ca1e2a
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Fixed lint WIDTH errors
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2021-06-09 20:58:20 -04:00 |
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David Harris
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90e5781471
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Start to parameterize number of PMP Entries
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2021-06-08 15:29:22 -04:00 |
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bbracker
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cc91c774a6
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Ah big ole merge! Passes sim-wally-batch and linting, so should be fine
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2021-06-08 12:41:25 -04:00 |
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bbracker
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e7e4105931
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* GPIO comprehensive testing
* MEPC more aware if M stage has actually committed
* UART interrupt testing progress
* UART added read IIR side effect of lowering THRE intr
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2021-06-08 12:32:46 -04:00 |
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David Harris
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ff62000e2c
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Second attept to commit refactoring config files
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2021-06-07 12:37:46 -04:00 |
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Kip Macsai-Goren
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49200bd922
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Cleaned up some unused signals
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2021-06-04 21:04:19 -04:00 |
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Kip Macsai-Goren
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22e8e06ac7
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moved privilege dfinitions into wally-constants, upgraded relevant includes
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2021-06-04 17:55:07 -04:00 |
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Kip Macsai-Goren
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1ae529c450
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restructured so that pma/pmp are a part of mmu
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2021-06-04 17:05:07 -04:00 |
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David Harris
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a26bf37be8
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Started MMU
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2021-06-04 11:59:14 -04:00 |
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bbracker
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2c77a13c08
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fixed InstrValid signals and implemented less costly MEPC loading
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2021-06-02 10:03:19 -04:00 |
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bbracker
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39ae743543
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turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
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2021-05-28 23:11:37 -04:00 |
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