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Simplified tlbmixer mux to and-or

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This commit is contained in:
David Harris 2021-07-08 23:34:24 -04:00
parent 74b6d13195
commit 5c2f774c35
2 changed files with 2 additions and 2 deletions
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2
wally-pipelined/src/mmu/tlbcontrol.sv
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@ -122,5 +122,5 @@ module tlbcontrol #(parameter TLB_ENTRIES = 8,
endgenerate
assign TLBHit = CAMHit & TLBAccess;
assign TLBMiss = ~TLBHit & ~TLBFlush & Translate & TLBAccess;
assign TLBMiss = ~CAMHit & ~TLBFlush & Translate & TLBAccess;
endmodule

2
wally-pipelined/src/privileged/csrs.sv
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@ -93,7 +93,7 @@ module csrs #(parameter
if (`MEM_VIRTMEM)
flopenr #(`XLEN) SATPreg(clk, reset, WriteSATPM, CSRWriteValM, SATP_REGW);
else
assign SATP_REGW = 0;
assign SATP_REGW = 0; // hardwire to zero if virtual memory not supported
if (`BUSYBEAR == 1)
flopenl #(32) SCOUNTERENreg(clk, reset, WriteSCOUNTERENM, {CSRWriteValM[31:2],1'b0,CSRWriteValM[0]}, 32'b0, SCOUNTEREN_REGW);
else if (`BUILDROOT == 1)