Katherine Parry
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6216bd7172
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FPU control signals changed and FMA works
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2021-06-28 18:53:58 -04:00 |
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bbracker
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4e09793a9a
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ah merge; I checked and this does pass all of regression except lints
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2021-06-25 07:37:06 -04:00 |
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Katherine Parry
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bc8d660bc5
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FPU forwarding reworked pt.1
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2021-06-24 18:39:18 -04:00 |
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bbracker
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ced5039776
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Revert "fixed forwarding"
This reverts commit 0f4a4a6ade.
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2021-06-24 17:39:37 -04:00 |
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bbracker
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0f4a4a6ade
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fixed forwarding
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2021-06-24 11:20:21 -04:00 |
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Katherine Parry
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03aea055fa
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FMV.X.D imperas test passes
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2021-05-24 14:44:30 -04:00 |
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Katherine Parry
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71e4a10efb
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FMV.D.X imperas test passes
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2021-05-20 22:17:59 -04:00 |
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Ross Thompson
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cdb7d15709
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Fixed bugs with the csr interacting with StallW. StallW is required to pervent updating a csr. Now have a working branch predictor and performance counters to track the number of commited branches and mispredictions.
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2021-03-24 15:56:55 -05:00 |
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Shreya Sanghai
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f35d3b39c8
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removed unnecesary PC registers in ifu
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2021-03-18 16:31:21 -04:00 |
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Ross Thompson
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619bbd9d83
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Merge branch 'bp' into main
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
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2021-03-04 13:35:46 -06:00 |
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David Harris
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6f4e8b723e
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Initial (untested) implementation of lr and sc
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2021-03-01 00:09:45 -05:00 |
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Ross Thompson
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6191fcb1af
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Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data.
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2021-02-26 20:12:27 -06:00 |
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David Harris
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0258901865
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Cleaned out unused signals
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2021-02-26 09:17:36 -05:00 |
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David Harris
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cd4ba8831c
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Merged bus into main
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2021-02-25 00:28:41 -05:00 |
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David Harris
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adc5d5bc1a
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Added MUL
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2021-02-15 22:27:35 -05:00 |
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David Harris
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33110ed636
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Data memory bus integration
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2021-02-07 23:21:55 -05:00 |
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David Harris
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756352f129
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Minor tweaks
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2021-02-02 19:44:37 -05:00 |
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David Harris
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429f48e766
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Rename ifu/dmem/ebu signals to match uarch diagram
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2021-02-02 15:09:24 -05:00 |
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David Harris
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229bde5953
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Moved LoadStall generation to IEU
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2021-02-02 13:42:23 -05:00 |
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David Harris
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bb83fda1d8
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Moved writeback pipeline registers from datapth into DMEM and CSR
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2021-02-02 13:02:31 -05:00 |
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David Harris
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07af481b67
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Reorganized src hierarchically
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2021-01-30 11:50:37 -05:00 |
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