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292 Commits

Author SHA1 Message Date
Ross Thompson
db635e3ad2 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-25 16:01:02 -05:00
David Harris
302a7fa294 Extended HADDR to PA_BITS 2022-08-25 13:11:36 -07:00
Ross Thompson
179aec3616 Still not working with rv32ic. 2022-08-25 15:03:54 -05:00
Ross Thompson
3b612d6201 Possible fixes for earily messup of rv32ic and rv64ic configs. 2022-08-25 14:42:08 -05:00
Ross Thompson
e605ef57dc BROKEN. Don't use this commit. 
Issue running cacheless with bus.
 2022-08-25 11:02:46 -05:00
Ross Thompson
b0aea77b20 Added generate around uncore. 2022-08-25 10:35:24 -05:00
David Harris
f7209627c2 removed simpleram and modified dtim to use bram1p1rw 2022-08-25 03:39:57 -07:00
David Harris
562be633ab Stripped write capaibilty out of rom_ahb 2022-08-24 17:23:08 -07:00
Ross Thompson
769af32f2a Renamed RAM to UNCORE_RAM. 2022-08-24 18:09:07 -05:00
Ross Thompson
fc22e807e2 Merged testbench-fpga into testbench. 
Modified SDC to simplify LimitTimers.  LimitTimers needs to be 0 for implmementation and 1 for simulation.
 2022-08-24 17:52:25 -05:00
Ross Thompson
4a371b6829 added SD card and external ram to common testbench. 2022-08-24 13:27:18 -05:00
Ross Thompson
51adf6cba9 Modified the lsu/ifu memory configurations. 2022-08-24 12:35:15 -05:00
David Harris
7fcc852687 Q depends on D 2022-08-23 08:29:59 -07:00
David Harris
e714b75888 LSU minor edits 2022-08-23 07:35:47 -07:00
David Harris
16a92eaf10 Updated testbench assertions. 2022-08-23 07:23:24 -07:00
Ross Thompson
ebe4339953 Updated fpga test bench. 
Solved read delay cache bug.  Introduced during cache optimizations.
 2022-08-21 15:59:54 -05:00
Ross Thompson
82cce9a627 Updated fpga testbench. 2022-08-21 14:07:26 -05:00
Katherine Parry
9549c23f45 sqrt tests in regression uncommented and pass 2022-08-07 23:38:10 +00:00
Katherine Parry
cb0c1b7488 radix-2 1 copy passes testfloat 2022-08-06 22:54:05 +00:00
David Harris
898dbc8e74 Completed PLIC-S tests. Regression working. This completes peripheral tests. 2022-08-03 09:33:56 -07:00
David Harris
7e5b78f240 plic-s debug 2022-08-03 12:33:09 +00:00
David Harris
257107f908 Partitioned fma into separate files 2022-08-01 18:07:38 +00:00
David Harris
75a265159b Increased timeout threshold to avoid timeout building riscof tests on slow machine 2022-07-27 04:05:21 +00:00
David Harris
9ecef0c4cd fixed testbench merge comflict 2022-07-26 06:21:46 -07:00
David Harris
2d7f4b133c More work toward riscof tests 2022-07-26 06:19:13 -07:00
David Harris
766252db1b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-25 23:29:08 +00:00
David Harris
5c54c5b521 Added rv32f tests to RV64gc 2022-07-25 23:29:05 +00:00
David Harris
c6a58eb5b6 Tests making successfully except for rv32gc_arch32f, which has FLEN=64 and tries using fld/fsd 2022-07-25 16:23:10 -07:00
Ross Thompson
8193946996 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-23 08:41:59 -05:00
Katherine Parry
b3d932cd61 divider sizes reworked to match book 2022-07-22 22:02:04 +00:00
Daniel Torres
24828db612 changes to test.vh for compatability 2022-07-22 15:00:48 -07:00
Daniel Torres
4198145ce2 added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail 2022-07-22 14:58:55 -07:00
slmnemo
ba2dcf6da4 fixed error in tests.vh 2022-07-22 14:55:55 -07:00
slmnemo
ec1ed5bd94 Added UART test to peripheral test 2022-07-22 14:55:34 -07:00
Daniel Torres
574e603d69 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-22 13:52:19 -07:00
Daniel Torres
139e657fcc commented out embench test that should be commented out 2022-07-22 13:52:13 -07:00
slmnemo
cb16a75119 Added PLIC test to regression 2022-07-22 12:35:37 -07:00
Daniel Torres
0e75142ef4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-22 11:16:09 -07:00
Daniel Torres
95fdd408ee commiting current changes to riscof wally tests 2022-07-22 11:14:04 -07:00
slmnemo
df568fd202 Added PLIC and UART tests and new functions to the test library 2022-07-22 07:10:39 -07:00
Daniel Torres
8dcb794bbb added support for new version of riscof and arch tests, now supports tests that can be compiled for both rv32 and rv64 2022-07-21 20:58:58 -07:00
Daniel Torres
9421b77613 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-21 12:50:04 -07:00
Daniel Torres
a8faddf81f removed ugly /ref/Ref from tests.vh, added back d_fsd-align-01.S and d_fld-align-01.S tests to tests.vh, updated makefile to fix the riscof issues and fix fld fsd tests, updated testbench.sv for comptability with changes 2022-07-21 12:47:51 -07:00
Katherine Parry
fbe8bb2298 radix-4 division integrated into srt - not tested 2022-07-21 19:38:06 +00:00
Katherine Parry
7950a675ea added input enables and improved forwarding 2022-07-21 01:20:06 +00:00
Daniel Torres
5b1adc7a67 commented out embench 2.0 tests 2022-07-19 13:36:18 -07:00
Katherine Parry
514674417e moved Se into execute stage 2022-07-19 01:10:10 +00:00
Katherine Parry
cce5fb8dfd moved Ss to execute stage 2022-07-18 20:48:56 +00:00
Katherine Parry
7268b4b334 removed underflow from inexactct calculation 2022-07-18 17:51:18 +00:00
Katherine Parry
0210718f19 renamed signals in ocde to match book 2022-07-18 17:31:17 +00:00