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Author SHA1 Message Date
David Harris
ca61cff33f CSR code cleanup 2023-04-27 14:12:57 -07:00
David Harris
a929656d9a Renamed byteUnit to byteop 2023-04-27 14:10:46 -07:00
David Harris
6a5895e09f Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-27 07:30:07 -07:00
David Harris
a0e473b2e6 Merge pull request #282 from ross144/main 
Arty A7 board support, ImperasDV linux boot, CVW_v0.9 tag
 2023-04-27 07:23:10 -07:00
David Harris
65d537a781 Merge pull request #279 from ACWright256/main 
Excluded and added coverage for WFI test case.
 2023-04-27 07:19:02 -07:00
Alexa Wright
09095422d0 Merge branch 'openhwgroup:main' into main 2023-04-26 16:26:30 -07:00
Alexa Wright
6ee8a9c0bd Added better comment for the exclusion in privdec.sv 2023-04-26 16:25:55 -07:00
David Harris
0eb8dd7935 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-26 15:40:11 -07:00
David Harris
ea3e3a1469 Merge pull request #283 from SydRiley/main 
Resolving unpackinput coverage issue with BadNaNBox, and increasing ifu and lsu coverage% through exclusions
 2023-04-26 15:40:01 -07:00
Sydeny
6415a5f0b2 For ifu and lsu exclusions added missing row numbers 2023-04-26 15:30:22 -07:00
Ross Thompson
212fee3613 Modified the imperas linux scripts so they run without reporting hundreds of gigabytes of data. 2023-04-26 17:29:57 -05:00
Ross Thompson
a263e5c9f6 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-26 17:27:52 -05:00
Sydeny
f49acd1293 Exclusion in the ifu and lsu to increase coverage, added missing row numbers 2023-04-26 15:26:39 -07:00
Sydeny
1a04ffcca9 Excluding untoggled signals in ifu and lsu, ifu coverage from 83.68% to 84.06% and lsu from 93.45% to 93.58% 2023-04-26 14:37:55 -07:00
Sydeny
5bcd57dab9 Addressing Redundant logic around BadNanBox, fpu coverage from 96.61% to 96.77% 2023-04-26 14:35:43 -07:00
David Harris
7cc26861cd Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-26 05:53:42 -07:00
David Harris
465f121c35 Merge pull request #280 from AlecVercruysse/coverage5 
100% D$ coverage
 2023-04-26 05:52:58 -07:00
Sydeny
cda71bea3f Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-26 03:00:25 -07:00
Sydeny
e5b3172cc9 added comments to exclusions 2023-04-26 03:00:13 -07:00
Alec Vercruysse
5612f30029 Cacheway Exclude FlushStage=1 when SetValidWay=1 
We determined that this case is not hit even for i$, so this
case is also excluded separately for i$. It could be a better
idea to remove the ~FlushStage check completely (if we're sure).

My reasoning for this one is written as a comment in the exclusion
script: since a pipeline stall is asserted by the cache in the fetch
stage (which happens before going into the WRITE_LINE state and
asserting SetValidWay), there seems to be no way to trigger
a FlushStage (FlushW for D$) while the stallM is active.
 2023-04-25 20:30:46 -07:00
David Harris
57fdc6d79d Merge pull request #278 from liamchalk00/main 
pmpaddr0 and pmpaddr2 test cases
 2023-04-25 20:16:11 -07:00
Alexa Wright
59d913949f Excluded and added coverage for WFI test case. 2023-04-25 17:06:57 -07:00
Alec Vercruysse
857956ac1e Cacheway exclude SelFlush=0 while FlushWay=0 in FlushWayEn assign 
FlushWay is always 1 for one way, but by default it is only 1 for
way 0.

The logic that advances FlushWay to ways 1, 2, and 3 only does so
on a subset of conditions that SelFlush is high (in cachefsm), so
this is unreachable for cachways 1-3.
 2023-04-25 17:02:53 -07:00
Alec Vercruysse
c19ed1990f extend invalidatecache d$ exclusion to statement coverage 2023-04-25 17:00:13 -07:00
Liam
7bf2ee5418 pmpaddr0 and pmpaddr2 test cases 
Writing 0x00170000 and 0x17000000 to pmpaddr0 and pmpaddr2.
Increased IFU coverage from 83.53% to 83.68% and LSU coverage from 93.29% to 93.45%.
 2023-04-25 15:37:04 -07:00
Ross Thompson
6907f0ccc1 FPGA makefile update. 2023-04-25 16:24:26 -05:00
David Harris
a5087818ba Commented about Sstvecd trap vector alignment 2023-04-24 12:20:33 -07:00
David Harris
ee6a3f49f0 Added M suffix in atomic 2023-04-24 12:19:56 -07:00
David Harris
e73922d34d Merge pull request #275 from dherreravicioso/main 
Excluded coverage for impossible cases in wficountreg and status.MPRV
 2023-04-24 12:18:55 -07:00
Diego Herrera Vicioso
d29dc30288 Excluded coverage for impossible cases in wficountreg and status.MPRV 2023-04-24 02:06:53 -07:00
Ross Thompson
a353bbc3f1 Merge pull request #272 from davidharrishmc/dev 
fdivsqrt coverage and fix bug of not trapping on access to odd-numbered pmpcfg
 2023-04-23 12:22:14 -05:00
David Harris
52f49ed24d Fault on writes to odd-numbered PMPCFG in RV64 2023-04-22 15:32:39 -07:00
David Harris
3b299fb77a Removed unproven fdivsqrt exclusion 2023-04-22 15:27:05 -07:00
David Harris
086556310c Attempted to cause interrupt during fdivsqrt. Fixed enabling fpu in fpu.S. Fdivsqrt exclusions for coverage. 2023-04-22 12:22:45 -07:00
David Harris
063e41806e Fixted syntax error in exclusion. Arbitrarily picked -e 1; fix if this isn't right 2023-04-22 10:07:48 -07:00
David Harris
69cc0b8bf3 test plan update 2023-04-22 09:38:14 -07:00
David Harris
a8acd60d71 Merge pull request #270 from liamchalk00/main 
pmpcfg test cases
 2023-04-22 08:41:11 -07:00
Liam
c2f441724b pmpcfg test cases 
Increased IFU coverage from 83.37% to 83.53% and LSU coverage from 93.14% to 93.28%.
 2023-04-21 20:43:37 -07:00
Ross Thompson
89065009ef Merge pull request #266 from davidharrishmc/dev 
FDivSqrt cleanup
 2023-04-21 20:23:23 -05:00
Ross Thompson
fa59c196de Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-21 12:46:22 -05:00
Ross Thompson
f22e6d0e48 Updated fpga Makefile to work with both the Arty and VCU platforms. 2023-04-21 11:08:35 -05:00
David Harris
8a59a4ce94 fdivsqrt cleanup 2023-04-20 17:35:01 -07:00
David Harris
86107e6136 continued cleanup 2023-04-20 16:48:23 -07:00
David Harris
33c0f64457 Reordered fdivsqrtpreproc to follow logic 2023-04-20 16:38:47 -07:00
David Harris
2c47268f50 Started fdivsqrtpreproc flow organization 2023-04-20 16:25:19 -07:00
David Harris
f2ae770e17 Fmv h/q comments in controller 2023-04-20 16:24:58 -07:00
David Harris
9f90c9efeb Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-20 16:07:37 -07:00
David Harris
b9d641f13a Merge pull request #256 from cturek/main 
Simplifying fds to follow diagram
 2023-04-20 16:07:22 -07:00
David Harris
d772806000 Merge pull request #265 from Noah-G-L/main 
Add Coverage for TLB, MP, Global, ASID and Match
 2023-04-20 16:06:09 -07:00
Noah Limpert
a0e71c26cb Add in a test that makes match 3 = 0 for all tlb lines 2023-04-20 14:50:06 -07:00