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9,153 Commits 4 Branches 2 Tags 53 MiB
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9153 Commits

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Author SHA1 Message Date
Jordan Carlin
5003cd56a8 Fix environment variables 2024-06-22 16:05:20 -07:00
Jordan Carlin
0e22c99467 Initial attempt at unified script 2024-06-22 13:07:34 -07:00
Jordan Carlin
2e55213286 Update install script comments and clean up packages. 2024-06-22 12:37:30 -07:00
Jordan Carlin
ad18734125 Update ubuntu toolchain install to match new red hat form in preparation for merging of scripts. 2024-06-22 12:37:25 -07:00
Jordan Carlin
9fc9e3c23d red hat install script syntax updates and allow for overriding of $RISCV directory 2024-06-22 12:37:20 -07:00
Jordan Carlin
55225f0d00 Red Hat family distro detection improvements 2024-06-22 12:37:15 -07:00
Jordan Carlin
2f7205b278 code style fixes 2024-06-22 12:36:56 -07:00
Jordan Carlin
b646dca8f6 Check if repo cloned but tool not installed (if there was an error and the script is being rerun), and install if so 2024-06-22 12:36:56 -07:00
Jordan Carlin
bcc01b78d6 red hat install script checks distro & version to determine what to install. Groundwork laid for ubuntu in same file. 2024-06-22 12:34:09 -07:00
Jordan Carlin
f682a71e24 Update to use EPEL package repo for ccache and gperftools 2024-06-22 12:32:57 -07:00
Jordan Carlin
2f55ac1cc7 Update red hat install script to only install each tool if it is the first time or if there are updates 2024-06-22 12:32:57 -07:00
Kevin Kim
eeea783da0 lint 2024-06-21 23:15:34 -07:00
Kevin Kim
4877633977 lint fixes tests vh 2024-06-21 22:16:09 -07:00
Kevin Kim
19f0cf7a35 putting back tests in tests vh 2024-06-21 21:51:44 -07:00
Kevin Kim
e6dc50308a integer postprocessing hardware matches diagram 2024-06-21 21:50:55 -07:00
Kevin Kim
00bf3faa9c changed intdivb width 2024-06-21 21:31:19 -07:00
Jordan Carlin
b76941d278
Use VCS built-in default macro instead of defining SIM_VCS 2024-06-21 15:17:59 -07:00
Kevin Kim
9a59c8e07f reduced bit widths for integer on fpu 2024-06-20 23:46:45 -07:00
Jordan Carlin
c568bdcfa3 initial version of red hat install toolchain 2024-06-20 20:47:18 -07:00
Ross Thompson
249d58244a It's working!!!!!! 2024-06-20 15:48:30 -07:00
Ross Thompson
1c6ebb86a3 Added some debug code to count frames sent to the ethernet mac and frames sent to the phy. 
Removed the external reset of the phy and now it always reliably starts in the same way.  The first 0x117 frames are always captured.
 2024-06-20 12:54:12 -07:00
Rose Thompson
e1fc44a5bf
Merge pull request #849 from davidharrishmc/dev 
lint cleanup and divider optimization
 2024-06-20 09:04:19 -07:00
David Harris
486e6ff0f6 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2024-06-20 08:43:48 -07:00
David Harris
d8d94eeafa
Merge pull request #808 from jordancarlin/main 
Update riscv-arch-test
 2024-06-20 08:43:41 -07:00
Jordan Carlin
90f5a4ef48
Only run fmsub_b15 for f_fma test 2024-06-20 07:48:33 -07:00
David Harris
25780f53ce Fixed Verilator testbench issue from FunctionName by rolling back to old if. PC=0 detection is disabled for now. 2024-06-20 00:57:58 -07:00
David Harris
27457f4ef4
Merge pull request #848 from ross144/main 
Covergen doesn't produce stores and riscv-dv only generates tests
 2024-06-20 00:10:33 -07:00
David Harris
0ab3f28991 Lint cleanup 2024-06-20 00:10:03 -07:00
Ross Thompson
e88a2f7eaa Merge branch 'main' of github.com:ross144/cvw into main 2024-06-19 15:14:28 -07:00
Ross Thompson
9e93f21990 Updated covergen to not include stores as they are incomplete. 
Modified makefile riscv-dv to not simulation only generate tests.
 2024-06-19 15:13:49 -07:00
David Harris
5f1ee1ac85 Fixed undriven signal in certain config 2024-06-19 15:12:35 -07:00
David Harris
e4febf25ae
Merge pull request #847 from ross144/main 
Partial fix for verilator +args. At least compiles.
 2024-06-19 14:27:39 -07:00
Rose Thompson
46ace521c6 Updated verilator makefile. 2024-06-19 16:25:31 -05:00
David Harris
9922b24cbe Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2024-06-19 14:13:08 -07:00
David Harris
1ffd30f2e1
Merge pull request #846 from ross144/main 
Removes *** from all system verilog
 2024-06-19 14:12:56 -07:00
Ross Thompson
685f4d3807 Removed the last of the ***. 2024-06-19 14:00:31 -07:00
Ross Thompson
2d8973df1d Updated wavefile to use new names. 2024-06-19 13:57:28 -07:00
Ross Thompson
64712d2243 Updated wave to match changes in testbench. 2024-06-19 13:51:50 -07:00
Ross Thompson
d368f2e77e Removed *** from testbench. 2024-06-19 13:51:37 -07:00
Ross Thompson
7f0ba87231 Updated comments in uart. 2024-06-19 13:51:30 -07:00
Ross Thompson
91c844ca45 Removed more *** from camline and csrc. 2024-06-19 12:31:50 -07:00
Ross Thompson
576f1b9e59 Moved the *** from trap to an issue. 2024-06-19 12:31:24 -07:00
Ross Thompson
9b6b6617af Cleaned up hptw. 2024-06-19 12:02:56 -07:00
Ross Thompson
24916d42e2 Refactored TLBMiss and TLBMissOrUpdateA(D) to simplify spill, ifu, lsu, and hptw. 2024-06-19 11:40:02 -07:00
Ross Thompson
71f267a17a Added InstrUpdateDAF to the HPTW. 2024-06-19 11:09:49 -07:00
Ross Thompson
77523c52c2 LSU no longer has ***. 2024-06-19 10:56:07 -07:00
Ross Thompson
5e5ca0809f Removed more *** from lsu and updated assertions for dtim. 2024-06-19 10:52:51 -07:00
Ross Thompson
4911642427 Removed *** and updated comments for bpred and align. 2024-06-19 10:31:44 -07:00
Ross Thompson
f0e5bbef0c Removed remaining *** from IFU. 2024-06-19 09:52:40 -07:00
Ross Thompson
cc58bfdcf3 Removed more *** from the ifu. 2024-06-19 09:49:17 -07:00