Ross Thompson
c83f0a2e99
Removed unused logic in icache.
2021-08-26 10:49:54 -05:00
Ross Thompson
642efbb563
Converted the icache type from logic to state type.
2021-08-26 10:41:42 -05:00
Ross Thompson
32ec457e09
Removed the hardware page table walker fault state from the icache so that the icache will only unstall CPU for 1 cycle.
...
In the dcache we added a register to save the load read data in the event an itlb miss occurs concurrently with
the load in the memory stage. Under this situation we need to record the load ReadDataM into a temporary register,
SavedReadDataM. At this time the CPU is stall; however the walker is going to change the address in the dcache
which destroys this data. When leaving the PTW_READY state via a walker instruction fault or ITLB write we select
this SavedReadDataM so that the CPU can capture it.
2021-07-22 19:42:19 -05:00
Ross Thompson
42fe5ceee3
Cleaned up icache and dcache.
2021-07-22 11:06:44 -05:00
Ross Thompson
6abd23a61d
Lint passes, but I only hope to have loads working. Stores, lr/sc, atomic, are not fully implemented.
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Also faults and the dcache ptw interlock are not implemented.
2021-07-09 15:16:38 -05:00
Ross Thompson
4c5aee3042
This d cache fsm is getting complex.
2021-07-08 15:26:16 -05:00
David Harris
d2e3e14cbc
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-07-04 18:55:24 -04:00
David Harris
57e1111df3
Gave names to for loops in generate blocks for ease of reference
2021-07-04 18:52:16 -04:00
bbracker
11606e96f1
ICacheCntrl now reacts differently to InstrPageFaultF vs ITLBWriteF
2021-07-04 18:17:06 -04:00
Ben Bracker
66692af57c
src/cache/ICacheCntrl.sv
2021-07-03 11:24:41 -05:00
Ben Bracker
d6c7dc02ed
fix ICache indenting
2021-07-03 11:11:07 -05:00
Ross Thompson
3dae02818c
OMG. It's working!
2021-07-01 17:37:53 -05:00
Ross Thompson
4530e43df6
The icache ptw interlock is actually correct now. There needed to be a 1 cycle delay.
2021-06-30 17:02:36 -05:00
Ross Thompson
2598f08782
Page table walker now walks the table.
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Added interlock so the icache stalls.
Page table walker not walking correctly, goes to fault state.
2021-06-29 22:33:57 -05:00
Ross Thompson
d5063bee7d
Updated icache to abhlite to use pa_bits length and moved F/D stage instr register to ifu from icache.
2021-06-23 15:13:56 -05:00
Ross Thompson
03084a4128
Icache now uses physical lenght bits rather than XLEN.
2021-06-21 16:41:09 -05:00
Ross Thompson
8ec5b0c4f1
Improved some names in icache.
2021-06-21 16:40:37 -05:00
Ross Thompson
bb756849a7
Revert "Icache now uses physical lenght bits rather than XLEN."
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This reverts commit d4de8a54a2
2021-06-19 08:58:34 -05:00
Ross Thompson
e4c932265d
Revert "Improved some names in icache."
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This reverts commit 22ea801edb
2021-06-19 08:58:32 -05:00
Ross Thompson
22ea801edb
Improved some names in icache.
2021-06-18 12:22:41 -05:00
Ross Thompson
d4de8a54a2
Icache now uses physical lenght bits rather than XLEN.
2021-06-18 12:02:59 -05:00
David Harris
5e01f71c52
disabled Verilator WIDTH warnings in ICCacheCntrl
2021-06-12 19:50:06 -04:00
David Harris
e231fc6b00
More verilator fixes, but bpred is broken
2021-06-09 21:03:03 -04:00
Ross Thompson
e200b4b5a4
Continued I-Cache cleanup.
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Removed strange mux on InstrRawD along with
the select logic.
2021-06-04 15:14:05 -05:00
Ross Thompson
2c16591396
Reorganized the icache names.
2021-06-04 12:53:42 -05:00
