Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity
4,902 Commits 5 Branches 2 Tags 53 MiB
c65becbae5
Commit Graph

4902 Commits

This Branch
This Branch
All Branches
Author SHA1 Message Date
David Harris
fc4146f409 Adding start signals for integer divider to fdivsqrt 2022-09-29 16:30:25 -07:00
Ross Thompson
47e936cab3 Renamed signals in EBU. 2022-09-29 18:29:38 -05:00
cturek
c72e2e5d49 Added integer inputs and flags to divsqrt 2022-09-29 23:08:27 +00:00
Ross Thompson
f9c4b32bd5 Simplification to EBU. 2022-09-29 18:06:34 -05:00
Ross Thompson
146ff6ff6a Fixed HTRANS not changing after accepting HREADY. This exposed a bug in uncore. 2022-09-29 11:54:03 -05:00
Ross Thompson
638e506d0b Hmm. the icache and ifu didn't have a CommittedF signals going back to the privileged unit. They probably should. If an interrupt occurred during the middle of an instruction fetch icache miss I think it would corrupt the icache. 2022-09-28 17:39:51 -05:00
Ross Thompson
87485ed237 Possible fix for ifu/lsu arbiration issue. 2022-09-27 17:24:35 -05:00
Ross Thompson
afc6934249 Possible fix to the bus cache interaction. 2022-09-27 11:34:33 -05:00
Ross Thompson
dfe6bdd06d Found a hidden bug in the cache to bus fsm interlock. 2022-09-26 17:41:30 -05:00
Ross Thompson
f24b0feeed renamed ahbmulticontroller to ebu. 2022-09-26 14:37:18 -05:00
Ross Thompson
fd47cf05c3 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-26 12:49:16 -05:00
Ross Thompson
fd2a8e621a Yesterday David and I found what is likely a bug in our AHB implementation. HTRANS was getting reset to 2 rather than 0 at the end of a burst transaction. This is fixed. 2022-09-26 12:48:26 -05:00
Kip Macsai-Goren
0d2fcaeab1 added xlen and endianness test edits. xlen passes but endinanness still won't make 2022-09-26 05:03:19 +00:00
Kip Macsai-Goren
4fa8b10315 added simple post processing script to give branch miss proportion in coremark log 2022-09-26 04:51:04 +00:00
David Harris
b5d2bbe7ca changed always_ff to always in sram1p1rw to fix testbench complaint 2022-09-25 19:56:40 -07:00
Ross Thompson
dcc00ef4b3 Renamed RW signals through the caches, bus interfaces, and IFU/LSU. 
CPU to $ is called LSURWM or IFURWF.
CPU to Bus is called BusRW
$ to Bus is called CacheBusRW.
 2022-09-23 11:46:53 -05:00
Ross Thompson
6a6686a34b Removed the write first sram model. 2022-09-22 16:12:08 -05:00
Ross Thompson
8a6ca027c2 The valid and dirty bits match the SRAM implementation now. 2022-09-22 16:09:09 -05:00
Ross Thompson
29087812e1 Solved the sram write first / read first issue. Works correctly with read first now. 2022-09-22 14:16:26 -05:00
Ross Thompson
f74d21e063 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-21 18:24:06 -05:00
Ross Thompson
cd5b8be78f Cleaned up the IFU and LSU around dtim and irom address calculation. 2022-09-21 18:23:56 -05:00
David Harris
cfa83fdd98 For radix 4 division, fixed initial C and then could remove unexplained shift from divshiftcalc 2022-09-21 13:30:35 -07:00
David Harris
fce927810a Fixed testbench-fp to support all again 2022-09-21 13:19:48 -07:00
David Harris
f08d5b23d5 Eliminated store after store stall when no cache; simplified divshiftcalc logic. 2022-09-21 13:02:34 -07:00
Ross Thompson
f83d640068 Updated IROMAdr logic. 2022-09-21 12:42:43 -05:00
Ross Thompson
0294ca0469 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-21 12:36:52 -05:00
Ross Thompson
cdc80c1f28 Moved other SRAMs to generic/mem. 2022-09-21 12:36:03 -05:00
David Harris
3b0714b059 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-21 10:35:11 -07:00
David Harris
1c8581dd6d Simplified shipping in divshiftcalc; enhanced testbench-fp to be able to run all 32-bit tests generated by sqrttest 2022-09-21 10:35:08 -07:00
Ross Thompson
427db1f55f Renamed brom1p1r to rom1p1r. 
removed used file bram2p1r1w.sv.
 2022-09-21 12:31:20 -05:00
Ross Thompson
234cf7510e Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-21 12:20:12 -05:00
Ross Thompson
91fcca9d17 Merged together bram1p1rw with sram1p1rw as sram1p1rw. 
Fixed a major issue with the real SRAM implemenation.
 2022-09-21 12:20:00 -05:00
Ross Thompson
d6fa8d51d7 Modified sram1p1rw to support 3 different implementation styles. 
SRAM, Read first, and Write first.
 2022-09-21 11:26:00 -05:00
David Harris
f87e15388a commented SpecialCase 2022-09-21 05:02:08 -07:00
David Harris
b21e36a788 Added SpecialCaseReg to hold SpecialCase for fdivsqrtpostproc 2022-09-21 04:55:43 -07:00
David Harris
437fd52bf6 Gated sticky bit in fdiv with SpecialCase 2022-09-20 20:05:00 -07:00
David Harris
cf5c513221 Restored radix 2 to pass regression 2022-09-20 19:30:16 -07:00
David Harris
9c8edb9cb6 renamed u to udigit to avoid conflict with U 2022-09-20 19:29:23 -07:00
cturek
e8f2715a81 Fixed R4 Sqrt overshifting 2022-09-21 00:05:36 +00:00
cturek
49a1259cf9 Fixed fgen4 2022-09-20 20:00:01 +00:00
Ross Thompson
c73fae8a96 Merge branch 'tempMain' into main 2022-09-20 13:57:38 -05:00
Ross Thompson
1c2e47e137 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-20 11:56:53 -05:00
Ross Thompson
b2f4d4aaa7 Added chip enables to sram. 2022-09-20 10:49:14 -05:00
David Harris
33af1f97f7 Define LOGNORMSHIFTSZ 2022-09-20 08:31:57 -07:00
Ross Thompson
7470bf7c7c Added comment. 2022-09-20 09:49:53 -05:00
Ross Thompson
ea6b687f7c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-09-20 09:47:16 -05:00
David Harris
811f498f63 renamed q to u for unified digit selection 2022-09-20 04:35:14 -07:00
David Harris
705a2bd97b Removed D2 and D2b from radix2 stage 2022-09-20 04:20:38 -07:00
David Harris
c77ec2aa9c Simplified UM initialization 2022-09-20 04:18:12 -07:00
David Harris
956011b40b fdivsqrtfgen4 comments 2022-09-20 04:13:21 -07:00