87 Commits

Author	SHA1	Message	Date
David Harris	d2de84a456	Added parity and stop bit tests to UART	2022-07-28 04:35:51 +00:00
slmnemo	0bfc3fda1b	Fixed UART FIFO bugs and added FIFO tests	2022-07-22 17:13:19 -07:00
David Harris	07c946bb04	Reset MSR on read	2022-07-22 04:29:27 +00:00
slmnemo	bfa500234d	Fixed UART bug related to parity and MSR/LSR	2022-07-21 20:35:46 -07:00
David Harris	6e1d4ec4ed	restored intPending logic to be sticky for PLIC	2022-07-16 17:43:31 -07:00
David Harris	381f3298d8	Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc	2022-07-08 09:09:02 +00:00
David Harris	1ce0975366	Adjusting byte writes to RAM	2022-07-08 08:45:21 +00:00
David Harris	9b6d9666c5	Removed unused swbytemask from CLINT	2022-07-08 08:43:24 +00:00
David Harris	a599084b88	PLIC and UART passing tests on APB	2022-07-06 13:26:14 +00:00
David Harris	d73645944f	APB CLINT passing regression	2022-07-05 15:51:35 +00:00
David Harris	d033659beb	Modified uncore to use AHB bridge to GPIO	2022-07-05 05:02:21 +00:00
David Harris	e7fe7ad0c8	AHB bridge for gpio	2022-07-05 05:01:59 +00:00
David Harris	aa3dc8bfe1	Added comments to PLIC about likely bug	2022-07-05 05:00:29 +00:00
David Harris	2c4b86c703	Fixed typo in clint	2022-06-23 21:27:46 +00:00
David Harris	ceddc99ac9	Reset mtimecmp in clint	2022-06-23 21:20:55 +00:00
David Harris	8ea484a343	Cleanup on RAM module	2022-06-13 19:37:43 +00:00
David Harris	b7a7ca6eac	Typo in gpio reset	2022-06-13 19:37:05 +00:00
David Harris	e9ef9a5cb8	Fixed XOR logic in GPIO	2022-06-13 19:26:03 +00:00
slmnemo	4ff105f18c	Fixed lint error	2022-06-09 17:22:04 -07:00
David Harris	c836f37a08	New RAM for further testing	2022-06-09 23:50:43 +00:00
David Harris	dd4fa7c682	qslc_r4a2 generator	2022-06-09 17:26:47 +00:00
David Harris	5240bd1c90	Modified RAM for single-cycle latency	2022-06-08 02:06:00 +00:00
David Harris	3c8eafc8ee	Cleaned bram interface	2022-06-08 01:39:44 +00:00
David Harris	9e5ab4d378	Added ahbapbbridge and cleaning RAM	2022-06-08 01:31:34 +00:00
Ross Thompson	e2cf941a23	Possible plic fix?	2022-05-22 23:47:01 -05:00
Ross Thompson	c4f1a0362b	Fixed receive fifo ITNR bug.	2022-05-22 10:55:28 -05:00
Ross Thompson	92a2ad02db	Added more debug signals to uart.	2022-05-21 19:47:40 -05:00
David Harris	8166fd772e	Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt	2022-05-11 15:08:33 +00:00
David Harris	137b411bea	Removed M suffix from interrupts because they are generated asynchronously to pipeline	2022-05-11 14:41:55 +00:00
David Harris	9e47fca2b7	Changed loop variable in CLINT because of error only seen on VLSI	2022-05-03 10:10:28 +00:00
bbracker	9c1e398bb5	change how tristate I/O is spoofed in GPIO loopback test	2022-04-21 10:31:16 -07:00
David Harris	1e19cf9f14	Simplified profile for UART boot; added warnings on UART Rx errors	2022-04-21 04:54:45 +00:00
Kip Macsai-Goren	ced763beb6	Added GPIO loopback to let outputs cause interrupts	2022-04-18 07:22:49 +00:00
David Harris	22842816a8	LSU name cleanup	2022-04-18 03:18:38 +00:00
Ross Thompson	7135364d1a	Increased uart baud rate to 230400. ... Added uart signals to debugger.	2022-04-17 15:23:39 -05:00
Ross Thompson	22f2e88553	UART and clock speed changes to support 30Mhz.	2022-04-12 17:56:36 -05:00
Ross Thompson	5faa88acd5	Increazed fpga clock speed to 35Mhz. ... linux boot is much faster.	2022-04-05 15:09:49 -05:00
Ross Thompson	91e99f0d34	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-04 10:56:10 -05:00
Ross Thompson	077beb18dd	Constraint changes for 40Mhz wally.	2022-04-04 10:50:48 -05:00
Ross Thompson	400b5f7632	Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz.	2022-04-04 09:57:26 -05:00
Ross Thompson	38160fe6ea	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-03 17:56:55 -05:00
Ross Thompson	3db60a1cc1	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-02 16:39:54 -05:00
Ross Thompson	35e8c6bb9c	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-02 16:35:59 -05:00
Ross Thompson	48c49802b2	Fixed linting issues.	2022-04-01 15:20:45 -05:00
Ross Thompson	301f20052b	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-01 12:50:34 -05:00
Ross Thompson	19a8df9739	Added wave config ... added new signals to ILA.	2022-04-01 12:44:14 -05:00
bbracker	e09079d8b4	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-03-31 17:54:43 -07:00
bbracker	55df8bc3f7	fix lingering overrun error bug	2022-03-31 17:54:32 -07:00
Ross Thompson	48c862d536	Added PLIC to ILA.	2022-03-31 16:44:49 -05:00
Ross Thompson	da93d14050	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-03-31 16:30:55 -05:00