mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
This commit is contained in:
Ross Thompson
commit
35e8c6bb9c
@ -19,10 +19,10 @@ disassemble:
|
||||
# -cd ${DIS}/rootfs; cpio -id --nonmatching 'dev/console' < ../../rootfs.cpio
|
||||
|
||||
${DIS}/fw_jump.objdump: ${IMAGES}/fw_jump.elf
|
||||
riscv64-unknown-elf-objdump -D ${IMAGES}/fw_jump.elf >> ${DIS}/fw_jump.objdump
|
||||
riscv64-unknown-elf-objdump -S ${IMAGES}/fw_jump.elf >> ${DIS}/fw_jump.objdump
|
||||
|
||||
${DIS}/vmlinux.objdump: ${IMAGES}/vmlinux
|
||||
riscv64-unknown-elf-objdump -D ${IMAGES}/vmlinux >> ${DIS}/vmlinux.objdump
|
||||
riscv64-unknown-elf-objdump -S ${IMAGES}/vmlinux >> ${DIS}/vmlinux.objdump
|
||||
|
||||
${DIS}/vmlinux.objdump.addr: ${DIS}/vmlinux.objdump
|
||||
-cd ${DIS}; extractFunctionRadix.sh vmlinux.objdump
|
||||
|
||||
@ -42,6 +42,7 @@
|
||||
`define ZIFENCEI_SUPPORTED 1
|
||||
`define ZICOUNTERS_SUPPORTED 1
|
||||
`define COUNTERS 32
|
||||
`define DESIGN_COMPILER 0
|
||||
|
||||
// Microarchitectural Features
|
||||
`define UARCH_PIPELINED 1
|
||||
|
||||
1024
pipelined/config/rv32ia/BTBPredictor.txt
Normal file
1024
pipelined/config/rv32ia/BTBPredictor.txt
Normal file
File diff suppressed because it is too large
Load Diff
1024
pipelined/config/rv32ia/twoBitPredictor.txt
Normal file
1024
pipelined/config/rv32ia/twoBitPredictor.txt
Normal file
File diff suppressed because it is too large
Load Diff
135
pipelined/config/rv32ia/wally-config.vh
Normal file
135
pipelined/config/rv32ia/wally-config.vh
Normal file
@ -0,0 +1,135 @@
|
||||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
|
||||
`define FPGA 0
|
||||
`define QEMU 0
|
||||
`define DESIGN_COMPILER 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 32
|
||||
|
||||
// IEEE 754 compliance
|
||||
`define IEEE754 0
|
||||
|
||||
// IA
|
||||
`define MISA (32'h00000100 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 << 3 | 1 << 5)
|
||||
`define ZICSR_SUPPORTED 1
|
||||
`define ZIFENCEI_SUPPORTED 1
|
||||
`define COUNTERS 32
|
||||
`define ZICOUNTERS_SUPPORTED 1
|
||||
|
||||
// Microarchitectural Features
|
||||
`define UARCH_PIPELINED 1
|
||||
`define UARCH_SUPERSCALR 0
|
||||
`define UARCH_SINGLECYCLE 0
|
||||
// *** replace with MEM_BUS
|
||||
`define DMEM `MEM_CACHE
|
||||
`define IMEM `MEM_CACHE
|
||||
`define DBUS 1
|
||||
`define IBUS 1
|
||||
`define VIRTMEM_SUPPORTED 1
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
`define ITLB_ENTRIES 32
|
||||
`define DTLB_ENTRIES 32
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
`define DCACHE_NUMWAYS 4
|
||||
`define DCACHE_WAYSIZEINBYTES 4096
|
||||
`define DCACHE_LINELENINBITS 256
|
||||
`define ICACHE_NUMWAYS 4
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_LINELENINBITS 256
|
||||
|
||||
// Integer Divider Configuration
|
||||
// DIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define DIV_BITSPERCYCLE 4
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 64
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 32'h80000000
|
||||
|
||||
// Peripheral Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
`define BOOTROM_SUPPORTED 1'b1
|
||||
`define BOOTROM_BASE 34'h00001000
|
||||
`define BOOTROM_RANGE 34'h00000FFF
|
||||
`define RAM_SUPPORTED 1'b1
|
||||
`define RAM_BASE 34'h80000000
|
||||
`define RAM_RANGE 34'h07FFFFFF
|
||||
`define EXT_MEM_SUPPORTED 1'b0
|
||||
`define EXT_MEM_BASE 34'h80000000
|
||||
`define EXT_MEM_RANGE 34'h07FFFFFF
|
||||
`define CLINT_SUPPORTED 1'b0
|
||||
`define CLINT_BASE 34'h02000000
|
||||
`define CLINT_RANGE 34'h0000FFFF
|
||||
`define GPIO_SUPPORTED 1'b0
|
||||
`define GPIO_BASE 34'h10060000
|
||||
`define GPIO_RANGE 34'h000000FF
|
||||
`define UART_SUPPORTED 1'b1
|
||||
`define UART_BASE 34'h10000000
|
||||
`define UART_RANGE 34'h00000007
|
||||
`define PLIC_SUPPORTED 1'b1
|
||||
`define PLIC_BASE 34'h0C000000
|
||||
`define PLIC_RANGE 34'h03FFFFFF
|
||||
`define SDC_SUPPORTED 1'b0
|
||||
`define SDC_BASE 34'h00012100
|
||||
`define SDC_RANGE 34'h0000001F
|
||||
|
||||
// Bus Interface width
|
||||
`define AHBW 32
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
`define GPIO_LOOPBACK_TEST 1
|
||||
|
||||
// Hardware configuration
|
||||
`define UART_PRESCALE 1
|
||||
|
||||
// Interrupt configuration
|
||||
`define PLIC_NUM_SRC 10
|
||||
// comment out the following if >=32 sources
|
||||
`define PLIC_NUM_SRC_LT_32
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define TWO_BIT_PRELOAD "../config/rv32ia/twoBitPredictor.txt"
|
||||
`define BTB_PRELOAD "../config/rv32ia/BTBPredictor.txt"
|
||||
`define BPRED_ENABLED 1
|
||||
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define TESTSBP 0
|
||||
|
||||
`define REPLAY 0
|
||||
`define HPTW_WRITES_SUPPORTED 0
|
||||
1024
pipelined/config/rv64ia/BTBPredictor.txt
Normal file
1024
pipelined/config/rv64ia/BTBPredictor.txt
Normal file
File diff suppressed because it is too large
Load Diff
1024
pipelined/config/rv64ia/twoBitPredictor.txt
Normal file
1024
pipelined/config/rv64ia/twoBitPredictor.txt
Normal file
File diff suppressed because it is too large
Load Diff
136
pipelined/config/rv64ia/wally-config.vh
Normal file
136
pipelined/config/rv64ia/wally-config.vh
Normal file
@ -0,0 +1,136 @@
|
||||
//////////////////////////////////////////
|
||||
// wally-config.vh
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 4 January 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Specify which features are configured
|
||||
// Macros to determine which modes are supported based on MISA
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
|
||||
`define FPGA 0
|
||||
`define QEMU 0
|
||||
`define DESIGN_COMPILER 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 64
|
||||
|
||||
// IEEE 754 compliance
|
||||
`define IEEE754 0
|
||||
|
||||
// MISA RISC-V configuration per specification IA
|
||||
`define MISA (32'h00000100 | 1 << 20 | 1 << 18 | 1 << 12 | 1 << 0 | 1 << 3 | 1 << 5)
|
||||
`define ZICSR_SUPPORTED 1
|
||||
`define ZIFENCEI_SUPPORTED 1
|
||||
`define COUNTERS 32
|
||||
`define ZICOUNTERS_SUPPORTED 1
|
||||
|
||||
/// Microarchitectural Features
|
||||
`define UARCH_PIPELINED 1
|
||||
`define UARCH_SUPERSCALR 0
|
||||
`define UARCH_SINGLECYCLE 0
|
||||
`define DMEM `MEM_CACHE
|
||||
`define IMEM `MEM_CACHE
|
||||
`define DBUS 1
|
||||
`define IBUS 1
|
||||
`define VIRTMEM_SUPPORTED 1
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
|
||||
// TLB configuration. Entries should be a power of 2
|
||||
`define ITLB_ENTRIES 32
|
||||
`define DTLB_ENTRIES 32
|
||||
|
||||
// Cache configuration. Sizes should be a power of two
|
||||
// typical configuration 4 ways, 4096 bytes per way, 256 bit or more lines
|
||||
`define DCACHE_NUMWAYS 4
|
||||
`define DCACHE_WAYSIZEINBYTES 4096
|
||||
`define DCACHE_LINELENINBITS 256
|
||||
`define ICACHE_NUMWAYS 4
|
||||
`define ICACHE_WAYSIZEINBYTES 4096
|
||||
`define ICACHE_LINELENINBITS 256
|
||||
|
||||
// Integer Divider Configuration
|
||||
// DIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define DIV_BITSPERCYCLE 4
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 64
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 64'h0000000080000000
|
||||
|
||||
// Bus Interface width
|
||||
`define AHBW 64
|
||||
|
||||
// Peripheral Physiccal Addresses
|
||||
// Peripheral memory space extends from BASE to BASE+RANGE
|
||||
// Range should be a thermometer code with 0's in the upper bits and 1s in the lower bits
|
||||
|
||||
// *** each of these is `PA_BITS wide. is this paramaterizable INSIDE the config file?
|
||||
`define BOOTROM_SUPPORTED 1'b1
|
||||
`define BOOTROM_BASE 56'h00001000 // spec had been 0x1000 to 0x2FFF, but dh truncated to 0x1000 to 0x1FFF because upper half seems to be all zeros and this is easier for decoder
|
||||
`define BOOTROM_RANGE 56'h00000FFF
|
||||
`define RAM_SUPPORTED 1'b1
|
||||
`define RAM_BASE 56'h80000000
|
||||
`define RAM_RANGE 56'h7FFFFFFF
|
||||
`define EXT_MEM_SUPPORTED 1'b0
|
||||
`define EXT_MEM_BASE 56'h80000000
|
||||
`define EXT_MEM_RANGE 56'h07FFFFFF
|
||||
`define CLINT_SUPPORTED 1'b1
|
||||
`define CLINT_BASE 56'h02000000
|
||||
`define CLINT_RANGE 56'h0000FFFF
|
||||
`define GPIO_SUPPORTED 1'b1
|
||||
`define GPIO_BASE 56'h10060000
|
||||
`define GPIO_RANGE 56'h000000FF
|
||||
`define UART_SUPPORTED 1'b1
|
||||
`define UART_BASE 56'h10000000
|
||||
`define UART_RANGE 56'h00000007
|
||||
`define PLIC_SUPPORTED 1'b1
|
||||
`define PLIC_BASE 56'h0C000000
|
||||
`define PLIC_RANGE 56'h03FFFFFF
|
||||
`define SDC_SUPPORTED 1'b0
|
||||
`define SDC_BASE 56'h00012100
|
||||
`define SDC_RANGE 56'h0000001F
|
||||
|
||||
// Test modes
|
||||
|
||||
// Tie GPIO outputs back to inputs
|
||||
`define GPIO_LOOPBACK_TEST 1
|
||||
|
||||
// Hardware configuration
|
||||
`define UART_PRESCALE 1
|
||||
|
||||
// Interrupt configuration
|
||||
`define PLIC_NUM_SRC 10
|
||||
// comment out the following if >=32 sources
|
||||
`define PLIC_NUM_SRC_LT_32
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define TWO_BIT_PRELOAD "../config/rv64ia/twoBitPredictor.txt"
|
||||
`define BTB_PRELOAD "../config/rv64ia/BTBPredictor.txt"
|
||||
`define BPRED_ENABLED 1
|
||||
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define TESTSBP 0
|
||||
|
||||
`define REPLAY 0
|
||||
`define HPTW_WRITES_SUPPORTED 0
|
||||
File diff suppressed because it is too large
Load Diff
@ -62,7 +62,7 @@ tc = TestCase(
|
||||
grepstr="400100000 instructions")
|
||||
configs.append(tc)
|
||||
|
||||
tests64gc = ["arch64i", "arch64priv", "arch64c", "arch64m", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64m", "wally64a", "imperas64c", "wally64priv", "wally64periph"] # , "imperas64mmu" "wally64i", #, "testsBP64"]
|
||||
tests64gc = ["arch64i", "arch64priv", "arch64c", "arch64m", "arch64d", "imperas64i", "imperas64f", "imperas64d", "imperas64m", "wally64a", "imperas64c", "wally64periph"] # , "imperas64mmu" "wally64i", #, "testsBP64"]
|
||||
for test in tests64gc:
|
||||
tc = TestCase(
|
||||
name=test,
|
||||
|
||||
@ -27,7 +27,6 @@ add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/LoadPageFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/StoreAmoPageFaultM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/InterruptM
|
||||
add wave -noupdate -group HDU -expand -group traps /testbench/dut/core/priv/priv/trap/PendingInterruptM
|
||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/hzu/FlushF
|
||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushD
|
||||
add wave -noupdate -group HDU -group Flush -color Yellow /testbench/dut/core/FlushE
|
||||
@ -92,7 +91,7 @@ add wave -noupdate -group Bpred -group {branch update selection inputs} /testben
|
||||
add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassWrongNonCFI
|
||||
add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPRight
|
||||
add wave -noupdate -group Bpred -group {branch update selection inputs} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BPClassRightBPWrong
|
||||
add wave -noupdate -group Bpred -radix hexadecimal -childformat {{{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} -radix binary}} -subitemconfig {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} {-height 16 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} {-height 16 -radix binary}} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel
|
||||
add wave -noupdate -group Bpred -radix hexadecimal -childformat {{{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} -radix binary} {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} -radix binary}} -subitemconfig {{/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[6]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[5]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[4]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[3]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[2]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[1]} {-height 17 -radix binary} {/testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel[0]} {-height 17 -radix binary}} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRMuxSel
|
||||
add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNext
|
||||
add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRUpdateEN
|
||||
add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PHTUpdateAdr
|
||||
@ -214,7 +213,6 @@ add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/lsuvirtmem/SelReplayCPURequest
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/RAdr
|
||||
@ -383,7 +381,6 @@ add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/GPIOIntr
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADPLIC
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HRESPPLIC
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/HREADYPLIC
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/plic/plic/ExtIntM
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intClaim
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intEn
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intInProgress
|
||||
@ -391,11 +388,11 @@ add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/pl
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intPriority
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/intThreshold
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/nextIntPending
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/pendingArray
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/pendingMaxP
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/pendingPGrouped
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/pendingRequestsAtMaxP
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/requests
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/irqMatrix
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/priorities_with_irqs
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/max_priority_with_irqs
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/irqs_at_max_priority
|
||||
add wave -noupdate -group plic -expand -group internals /testbench/dut/uncore/plic/plic/threshMask
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HCLK
|
||||
add wave -noupdate -group GPIO /testbench/dut/uncore/gpio/gpio/HSELGPIO
|
||||
@ -425,21 +422,21 @@ add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIME
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/MTIMECMP
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/TimerIntM
|
||||
add wave -noupdate -group CLINT /testbench/dut/uncore/clint/clint/SwIntM
|
||||
add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HCLK
|
||||
add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HRESETn
|
||||
add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HSELUART
|
||||
add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HADDR
|
||||
add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HWRITE
|
||||
add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HWDATA
|
||||
add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HREADUART
|
||||
add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HRESPUART
|
||||
add wave -noupdate -group uart -group {Bus Connection} /testbench/dut/uncore/uart/uart/HREADYUART
|
||||
add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/LSR
|
||||
add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/MCR
|
||||
add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/MSR
|
||||
add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/RBR
|
||||
add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/TXHR
|
||||
add wave -noupdate -group uart -group Registers /testbench/dut/uncore/uart/uart/u/LCR
|
||||
add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HCLK
|
||||
add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HRESETn
|
||||
add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HSELUART
|
||||
add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HADDR
|
||||
add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HWRITE
|
||||
add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HWDATA
|
||||
add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HREADUART
|
||||
add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HRESPUART
|
||||
add wave -noupdate -group uart -expand -group {Bus Connection} /testbench/dut/uncore/uart/uart/HREADYUART
|
||||
add wave -noupdate -group uart -expand -group Registers -expand /testbench/dut/uncore/uart/uart/u/LSR
|
||||
add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uart/uart/u/MCR
|
||||
add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uart/uart/u/MSR
|
||||
add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uart/uart/u/RBR
|
||||
add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uart/uart/u/TXHR
|
||||
add wave -noupdate -group uart -expand -group Registers /testbench/dut/uncore/uart/uart/u/LCR
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/INTR
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxstate
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/txstate
|
||||
@ -448,6 +445,11 @@ add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/txbitsexpected
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxbitsreceived
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxbitsexpected
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxdata
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxoverrunerr
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxdataready
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxdataavailintr
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/RXBR
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/squashRXerrIP
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/rxshiftreg
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/SOUTbit
|
||||
add wave -noupdate -group uart /testbench/dut/uncore/uart/uart/u/SINsync
|
||||
@ -526,4 +528,4 @@ configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {0 ns} {496 ns}
|
||||
WaveRestoreZoom {0 ns} {208 ns}
|
||||
|
||||
@ -308,7 +308,10 @@ module uartPC16550D(
|
||||
if (fifoenabled) begin
|
||||
if (rxfifotail+1 < rxfifohead) rxfifotail <= #1 rxfifotail + 1;
|
||||
if (rxfifohead == rxfifotail +1) rxdataready <= #1 0;
|
||||
end else rxdataready <= #1 0;
|
||||
end else begin
|
||||
rxdataready <= #1 0;
|
||||
RXBR <= #1 {0, RXBR[9:0]}; // Ben 31 March 2022: I added this so that rxoverrunerr permanently goes away upon reading RBR (when not in FIFO mode)
|
||||
end
|
||||
end else if (~MEMWb & A == 3'b010) // writes to FIFO Control Register
|
||||
if (Din[1] | ~Din[0]) begin // rx FIFO reset or FIFO disable clears FIFO contents
|
||||
rxfifohead <= #1 0; rxfifotail <= #1 0;
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -1,3 +1,5 @@
|
||||
include ../../Makefile.include
|
||||
|
||||
RVTEST_DEFINES += -march=rv$(XLEN)ia # KMG: removed compressed instructions from privileged tests
|
||||
|
||||
$(eval $(call compile_template,-march=rv32iac -mabi=ilp32 -Drvtest_mtrap_routine=True -DXLEN=$(XLEN)))
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,990 @@
|
||||
00000aaa # Test 5.3.1.4: readback value from writing mie to enable interrupts
|
||||
00000001 # mcause from an instruction access fault
|
||||
00000000 # mtval of faulting instruction address (0x0)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000002 # mcause from an Illegal instruction
|
||||
00000000 # mtval of faulting instruction (0x0)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000003 # mcause from Breakpoint
|
||||
800003ec # mtval of breakpoint instruction adress (0x800003ec)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000004 # mcause from load address misaligned
|
||||
800003f5 # mtval of misaligned address (0x800003f5)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000005 # mcause from load access
|
||||
00000000 # mtval of accessed adress (0x0)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000006 # mcause from store misaligned
|
||||
80000411 # mtval of address with misaligned store instr (0x80000410)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000007 # mcause from store access
|
||||
00000000 # mtval of accessed address (0x0)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
0000000b # mcause from M mode ecall
|
||||
00000000 # mtval of ecall (*** defined to be zero for now)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000008 # mcause from U mode ecall
|
||||
00000000 # mtval of ecall (*** defined to be zero for now)
|
||||
00000080 # masked out mstatus.MPP = 00 (from U mode), mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000009 # mcause from S mode ecall
|
||||
00000000 # mtval of ecall (*** defined to be zero for now)
|
||||
00000880 # masked out mstatus.MPP = 01 (from S mode), mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
000007ec # value to indicate a vectored interrupts
|
||||
80000007 # mcause value from m time interrupt
|
||||
00000000 # mtval for mtime interrupt (0x0)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
000007ec # value to indicate a vectored interrupts
|
||||
80000001 # mcause value from m soft interrupt
|
||||
00000000 # mtval for msoft interrupt (0x0)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
000007ec # value to indicate a vectored interrupts
|
||||
8000000b # mcause value from m ext interrupt
|
||||
00000000 # mtval for mext interrupt (0x0)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
0000b309 # medeleg after attempted write of all 1's (only some bits are writeable)
|
||||
00000222 # mideleg after attempted write of all 1's (only some bits are writeable)
|
||||
00000001 # Test 5.3.1.4: mcause from an instruction access fault
|
||||
00000000 # mtval of faulting instruction address (0x0)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000002 # mcause from an Illegal instruction
|
||||
00000000 # mtval of faulting instruction (0x0)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000003 # mcause from Breakpoint
|
||||
800003ec # mtval of breakpoint instruction adress (0x800003ec)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000004 # mcause from load address misaligned
|
||||
800003f5 # mtval of misaligned address (0x800003f5)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000005 # mcause from load access
|
||||
00000000 # mtval of accessed adress (0x0)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000006 # mcause from store misaligned
|
||||
80000411 # mtval of address with misaligned store instr (0x80000410)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
00000007 # mcause from store access
|
||||
00000000 # mtval of accessed address (0x0)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
0000000b # mcause from M mode ecall
|
||||
00000000 # mtval of ecall (*** defined to be zero for now)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
000007ec # value to indicate a vectored interrupts
|
||||
80000007 # mcause value from time interrupt
|
||||
00000000 # mtval for mtime interrupt (0x0)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
000007ec # value to indicate a vectored interrupts
|
||||
80000001 # mcause value from m soft interrupt
|
||||
00000000 # mtval for msoft interrupt (0x0)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
000007ec # value to indicate a vectored interrupts
|
||||
0000000b # mcause value from m ext interrupt
|
||||
00000000 # mtval for mext interrupt (0x0)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
0000000b # mcause from M mode ecall from test termination
|
||||
00000000 # mtval of ecall (*** defined to be zero for now)
|
||||
00001880 # masked out mstatus.MPP = 11, mstatus.MPIE = 1, and mstatus.MIE = 0
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
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|
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|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
deadbeef
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
@ -25,7 +25,7 @@
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
s_file_begin:
|
||||
TRAP_HANDLER m
|
||||
|
||||
# Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in S mode.
|
||||
|
||||
|
||||
@ -25,7 +25,7 @@
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
s_file_begin:
|
||||
TRAP_HANDLER m
|
||||
|
||||
# Test 5.2.3.6: Test that all the machine mode CSR's are innaccessible for reads and writes in R mode.
|
||||
|
||||
|
||||
@ -25,7 +25,8 @@
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
s_file_begin:
|
||||
TRAP_HANDLER m
|
||||
|
||||
j test_loop_setup // begin test loop/table tests instead of executing inline code.
|
||||
|
||||
INIT_TEST_TABLE
|
||||
|
||||
@ -38,7 +38,8 @@
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
s_file_begin:
|
||||
TRAP_HANDLER m
|
||||
|
||||
j test_loop_setup // begin test loop/table tests instead of executing inline code.
|
||||
|
||||
INIT_TEST_TABLE
|
||||
|
||||
@ -25,7 +25,8 @@
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
s_file_begin:
|
||||
TRAP_HANDLER m
|
||||
|
||||
j test_loop_setup // begin test loop/table tests instead of executing inline code.
|
||||
|
||||
INIT_TEST_TABLE
|
||||
|
||||
@ -52,16 +52,128 @@ RVTEST_CODE_BEGIN
|
||||
// address for stack
|
||||
la sp, top_of_stack
|
||||
|
||||
// trap handler setup
|
||||
la x1, machine_trap_handler
|
||||
csrrw x4, mtvec, x1 // x4 reserved for "default" trap handler address that needs to be restored before halting this test.
|
||||
.endm
|
||||
|
||||
// Code to trigger traps goes here so we have consistent mtvals for instruction adresses
|
||||
// Even if more tests are added.
|
||||
.macro CAUSE_TRAP_TRIGGERS
|
||||
j end_trap_triggers
|
||||
|
||||
// The following tests involve causing many of the interrupts and exceptions that are easily done in a few lines
|
||||
// This effectively includes everything that isn't to do with page faults (virtual memory)
|
||||
|
||||
cause_instr_addr_misaligned:
|
||||
// cause a misaligned address trap
|
||||
auipc x28, 0 // get current PC, which is aligned
|
||||
addi x28, x28, 0x3 // add 1 to pc to create misaligned address
|
||||
jr x28 // cause instruction address midaligned trap
|
||||
ret
|
||||
|
||||
cause_instr_access:
|
||||
la x28, 0x0 // address zero is an address with no memory
|
||||
sw x1, -4(sp) // push the return adress ontot the stack
|
||||
addi sp, sp, -4
|
||||
jalr x28 // cause instruction access trap
|
||||
lw x1, 0(sp) // pop return adress back from the stack
|
||||
addi sp, sp, 4
|
||||
ret
|
||||
|
||||
cause_illegal_instr:
|
||||
.word 0x00000000 // a 32 bit zros is an illegal instruction
|
||||
ret
|
||||
|
||||
cause_breakpnt: // ****
|
||||
ebreak
|
||||
ret
|
||||
|
||||
cause_load_addr_misaligned:
|
||||
auipc x28, 0 // get current PC, which is aligned
|
||||
addi x28, x28, 1
|
||||
lw x29, 0(x28) // load from a misaligned address
|
||||
ret
|
||||
|
||||
cause_load_acc:
|
||||
la x28, 0 // 0 is an address with no memory
|
||||
lw x29, 0(x28) // load from unimplemented address
|
||||
ret
|
||||
|
||||
cause_store_addr_misaligned:
|
||||
auipc x28, 0 // get current PC, which is aligned
|
||||
addi x28, x28, 1
|
||||
sw x29, 0(x28) // store to a misaligned address
|
||||
ret
|
||||
|
||||
cause_store_acc:
|
||||
la x28, 0 // 0 is an address with no memory
|
||||
sw x29, 0(x28) // store to unimplemented address
|
||||
ret
|
||||
|
||||
cause_ecall:
|
||||
// *** ASSUMES you have already gone to the mode you need to call this from.
|
||||
ecall
|
||||
ret
|
||||
|
||||
cause_time_interrupt:
|
||||
// The following code works for both RV32 and RV64.
|
||||
// RV64 alone would be easier using double-word adds and stores
|
||||
li x28, 0x30 // Desired offset from the present time
|
||||
la x29, 0x02004000 // MTIMECMP register in CLINT
|
||||
la x30, 0x0200BFF8 // MTIME register in CLINT
|
||||
lw x7, 0(x30) // low word of MTIME
|
||||
lw x31, 4(x30) // high word of MTIME
|
||||
add x28, x7, x28 // add desired offset to the current time
|
||||
bgtu x28, x7, nowrap // check new time exceeds current time (no wraparound)
|
||||
addi x31, x31, 1 // if wrap, increment most significant word
|
||||
sw x31,4(x29) // store into most significant word of MTIMECMP
|
||||
nowrap:
|
||||
sw x28, 0(x29) // store into least significant word of MTIMECMP
|
||||
loop: j loop // wait until interrupt occurs
|
||||
ret
|
||||
|
||||
cause_soft_interrupt:
|
||||
la x28, 0x02000000 // MSIP register in CLINT
|
||||
li x29, 1 // 1 in the lsb
|
||||
sw x29, 0(x28) // Write MSIP bit
|
||||
ret
|
||||
|
||||
cause_ext_interrupt:
|
||||
li x28, 0x10060000 // load base GPIO memory location
|
||||
li x29, 0x1
|
||||
sw x29, 8(x28) // enable the first pin as an output
|
||||
sw x29, 28(x28) // set first pin to high interrupt enable
|
||||
sw x29, 40(x28) // write a 1 to the first output pin (cause interrupt)
|
||||
ret
|
||||
|
||||
end_trap_triggers:
|
||||
.endm
|
||||
|
||||
.macro TRAP_HANDLER MODE, VECTORED=1, DEBUG=0
|
||||
// MODE decides which mode this trap handler will be taken in (M or S mode)
|
||||
// Vectored decides whether interrumpts are handled with the vector table at trap_handler_MODE (1)
|
||||
// vs Using the non-vector approach the rest of the trap handler takes (0)
|
||||
// DEBUG decides whether we will print mtval a string with status.mpie, status.mie, and status.mpp to the signature (1)
|
||||
// vs not saving that info to the signature (0)
|
||||
|
||||
|
||||
// Set up the exception Handler, keeping the original handler in x4.
|
||||
la x1, trap_handler_\MODE\()
|
||||
ori x1, x1, \VECTORED // set mode field of tvec to VECTORED, which will force vectored interrupts if it's 1.
|
||||
|
||||
.if (\MODE\() == m)
|
||||
csrrw x4, \MODE\()tvec, x1 // x4 reserved for "default" trap handler address that needs to be restored before halting this test.
|
||||
.else
|
||||
csrw \MODE\()tvec, x1 // we only neet save the machine trap handler and this if statement ensures it isn't overwritten
|
||||
.endif
|
||||
|
||||
li a0, 0
|
||||
li a1, 0
|
||||
li a2, 0 // reset trap handler inputs to zero
|
||||
|
||||
// go to beginning of S file where we can decide between using the test data loop
|
||||
// or using the macro inline code insertion
|
||||
j s_file_begin
|
||||
la x29, 0x02004000 // MTIMECMP register in CLINT
|
||||
li x30, 0xFFFFFFFF
|
||||
sw x30, 0(x29) // set mtimecmp to 0xFFFFFFFF to really make sure time interrupts don't go off immediately after being enabled
|
||||
|
||||
j trap_handler_end_\MODE\() // skip the trap handler when it is being defined.
|
||||
|
||||
// ---------------------------------------------------------------------------------------------
|
||||
// General traps Handler
|
||||
@ -96,38 +208,77 @@ RVTEST_CODE_BEGIN
|
||||
// --------------------------------------------------------------------------------------------
|
||||
|
||||
|
||||
machine_trap_handler:
|
||||
.align 2
|
||||
trap_handler_\MODE\():
|
||||
j trap_unvectored_\MODE\() // for the unvectored implimentation: jump past this table of addresses into the actual handler
|
||||
// *** ASSUMES that a cause value of 0 for an interrupt is unimplemented
|
||||
// otherwise, a vectored interrupt handler should jump to trap_handler_\MODE\() + 4 * Interrupt cause code
|
||||
// No matter the value of VECTORED, exceptions (not interrupts) are handled in an unvecotred way
|
||||
j soft_interrupt_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
|
||||
j segfault_\MODE\() // 2: reserved
|
||||
j soft_interrupt_\MODE\() // 3: breakpoint
|
||||
j segfault_\MODE\() // 4: reserved
|
||||
j time_interrupt_\MODE\() // 5: load access fault
|
||||
j segfault_\MODE\() // 6: reserved
|
||||
j time_interrupt_\MODE\() // 7: store access fault
|
||||
j segfault_\MODE\() // 8: reserved
|
||||
j ext_interrupt_\MODE\() // 9: ecall from S-mode
|
||||
j segfault_\MODE\() // 10: reserved
|
||||
j ext_interrupt_\MODE\() // 11: ecall from M-mode
|
||||
// 12 through >=16 are reserved or designated for platform use
|
||||
|
||||
trap_unvectored_\MODE\():
|
||||
// The processor is always in machine mode when a trap takes us here
|
||||
// save registers on stack before using
|
||||
sw x1, -4(sp)
|
||||
sw x5, -8(sp)
|
||||
|
||||
// Record trap
|
||||
csrr x1, mcause // record the mcause
|
||||
csrr x1, \MODE\()cause // record the mcause
|
||||
sw x1, 0(x16)
|
||||
addi x6, x6, 4
|
||||
addi x16, x16, 4 // update pointers for logging results
|
||||
|
||||
.if (\DEBUG\() == 1) // record extra information (MTVAL, some status bits) about traps
|
||||
csrr x1, \MODE\()tval
|
||||
sw x1, 0(x16)
|
||||
addi x6, x6, 4
|
||||
addi x16, x16, 4
|
||||
|
||||
csrr x1, \MODE\()status
|
||||
.if (\MODE\() == m) // Taking traps in different modes means we want to get different bits from the status register.
|
||||
li x5, 0x1888 // mask bits to select MPP, MPIE, and MIE.
|
||||
.else
|
||||
li x5, 0x122 // mask bits to select SPP, SPIE, and SIE.
|
||||
.endif
|
||||
and x5, x5, x1
|
||||
sw x5, 0(x16) // store masked out status bits to the output
|
||||
addi x6, x6, 4
|
||||
addi x16, x16, 4
|
||||
|
||||
.endif
|
||||
|
||||
// Respond to trap based on cause
|
||||
// All interrupts should return after being logged
|
||||
csrr x1, \MODE\()cause
|
||||
li x5, 0x8000000000000000 // if msb is set, it is an interrupt
|
||||
and x5, x5, x1
|
||||
bnez x5, trapreturn // return from interrupt
|
||||
bnez x5, trapreturn_\MODE\() // return from interrupt
|
||||
// Other trap handling is specified in the vector Table
|
||||
slli x1, x1, 2 // multiply cause by 4 to get offset in vector Table
|
||||
la x5, trap_handler_vector_table
|
||||
la x5, exception_vector_table_\MODE\()
|
||||
add x5, x5, x1 // compute address of vector in Table
|
||||
lw x5, 0(x5) // fectch address of handler from vector Table
|
||||
jr x5 // and jump to the handler
|
||||
|
||||
segfault:
|
||||
segfault_\MODE\():
|
||||
lw x5, -8(sp) // restore registers from stack before faulting
|
||||
lw x1, -4(sp)
|
||||
j terminate_test // halt program.
|
||||
|
||||
trapreturn:
|
||||
trapreturn_\MODE\():
|
||||
// look at the instruction to figure out whether to add 2 or 4 bytes to PC, or go to address specified in a1
|
||||
csrr x1, mepc // get the mepc
|
||||
csrr x1, \MODE\()epc // get the mepc
|
||||
addi x1, x1, 4 // *** should be 2 for compressed instructions, see note.
|
||||
|
||||
|
||||
@ -151,13 +302,13 @@ trapreturn:
|
||||
// csrr x1, mepc // get the mepc again
|
||||
// addi x1, x1, 4 // add 4 to find the next instruction
|
||||
|
||||
trapreturn_specified:
|
||||
trapreturn_specified_\MODE\():
|
||||
// reset the necessary pointers and registers (x1, x5, x6, and the return address going to mepc)
|
||||
// so that when we return to a new virtual address, they're all in the right spot as well.
|
||||
|
||||
beqz a1, trapreturn_finished // either update values, of go to default return address.
|
||||
beqz a1, trapreturn_finished_\MODE\() // either update values, of go to default return address.
|
||||
|
||||
la x5, trap_return_pagetype_table
|
||||
la x5, trap_return_pagetype_table_\MODE\()
|
||||
slli a2, a2, 2
|
||||
add x5, x5, a2
|
||||
lw a2, 0(x5) // a2 = number of offset bits in current page type
|
||||
@ -189,54 +340,93 @@ trapreturn_specified:
|
||||
li a1, 0
|
||||
li a2, 0 // reset trapreturn inputs to the trap handler
|
||||
|
||||
trapreturn_finished:
|
||||
csrw mepc, x1 // update the mepc with address of next instruction
|
||||
trapreturn_finished_\MODE\():
|
||||
csrw \MODE\()epc, x1 // update the mepc with address of next instruction
|
||||
lw x5, -8(sp) // restore registers from stack before returning
|
||||
lw x1, -4(sp)
|
||||
mret // return from trap
|
||||
\MODE\()ret // return from trap
|
||||
|
||||
ecallhandler:
|
||||
ecallhandler_\MODE\():
|
||||
// Check input parameter a0. encoding above.
|
||||
// *** ASSUMES: that this trap is being handled in machine mode. in other words, that nothing odd has been written to the medeleg or mideleg csrs.
|
||||
li x5, 2 // case 2: change to machine mode
|
||||
beq a0, x5, ecallhandler_changetomachinemode
|
||||
beq a0, x5, ecallhandler_changetomachinemode_\MODE\()
|
||||
li x5, 3 // case 3: change to supervisor mode
|
||||
beq a0, x5, ecallhandler_changetosupervisormode
|
||||
beq a0, x5, ecallhandler_changetosupervisormode_\MODE\()
|
||||
li x5, 4 // case 4: change to user mode
|
||||
beq a0, x5, ecallhandler_changetousermode
|
||||
beq a0, x5, ecallhandler_changetousermode_\MODE\()
|
||||
// unsupported ecalls should segfault
|
||||
j segfault
|
||||
j segfault_\MODE\()
|
||||
|
||||
ecallhandler_changetomachinemode:
|
||||
ecallhandler_changetomachinemode_\MODE\():
|
||||
// Force mstatus.MPP (bits 12:11) to 11 to enter machine mode after mret
|
||||
li x1, 0b1100000000000
|
||||
csrs mstatus, x1
|
||||
j trapreturn
|
||||
csrs \MODE\()status, x1
|
||||
j trapreturn_\MODE\()
|
||||
|
||||
ecallhandler_changetosupervisormode:
|
||||
ecallhandler_changetosupervisormode_\MODE\():
|
||||
// Force mstatus.MPP (bits 12:11) to 01 to enter supervisor mode after mret
|
||||
li x1, 0b1100000000000
|
||||
csrc mstatus, x1
|
||||
csrc \MODE\()status, x1
|
||||
li x1, 0b0100000000000
|
||||
csrs mstatus, x1
|
||||
j trapreturn
|
||||
csrs \MODE\()status, x1
|
||||
j trapreturn_\MODE\()
|
||||
|
||||
ecallhandler_changetousermode:
|
||||
ecallhandler_changetousermode_\MODE\():
|
||||
// Force mstatus.MPP (bits 12:11) to 00 to enter user mode after mret
|
||||
li x1, 0b1100000000000
|
||||
csrc mstatus, x1
|
||||
j trapreturn
|
||||
csrc \MODE\()status, x1
|
||||
j trapreturn_\MODE\()
|
||||
|
||||
instrfault:
|
||||
instrpagefault_\MODE\():
|
||||
lw x1, -4(sp) // load return address int x1 (the address AFTER the jal into faulting page)
|
||||
j trapreturn_finished // puts x1 into mepc, restores stack and returns to program (outside of faulting page)
|
||||
j trapreturn_finished_\MODE\() // puts x1 into mepc, restores stack and returns to program (outside of faulting page)
|
||||
|
||||
illegalinstr:
|
||||
j trapreturn // return to the code after recording the mcause
|
||||
instrfault_\MODE\():
|
||||
lw x1, -4(sp) // load return address int x1 (the address AFTER the jal to the faulting address)
|
||||
j trapreturn_finished_\MODE\() // return to the code after recording the mcause
|
||||
|
||||
accessfault:
|
||||
illegalinstr_\MODE\():
|
||||
j trapreturn_\MODE\() // return to the code after recording the mcause
|
||||
|
||||
accessfault_\MODE\():
|
||||
// *** What do I have to do here?
|
||||
j trapreturn
|
||||
j trapreturn_\MODE\()
|
||||
|
||||
addr_misaligned_\MODE\():
|
||||
j trapreturn_\MODE\()
|
||||
|
||||
breakpt_\MODE\():
|
||||
j trapreturn_\MODE\()
|
||||
|
||||
soft_interrupt_\MODE\():
|
||||
li x5, 0x7EC // write 0x7EC (looks like VEC) to the output before the mcause and extras to indicate that this trap was handled with a vector table.
|
||||
sw x5, 0(x16)
|
||||
addi x6, x6, 4
|
||||
addi x16, x16, 4
|
||||
la x28, 0x02000000 // Reset by clearing MSIP interrupt from CLINT
|
||||
sw x0, 0(x28)
|
||||
j trap_unvectored_\MODE\()
|
||||
|
||||
time_interrupt_\MODE\():
|
||||
li x5, 0x7EC
|
||||
sw x5, 0(x16)
|
||||
addi x6, x6, 4
|
||||
addi x16, x16, 4
|
||||
la x29, 0x02004000 // MTIMECMP register in CLINT
|
||||
li x30, 0xFFFFFFFF
|
||||
sw x30, 0(x29) // reset interrupt by setting mtimecmp to 0xFFFFFFFF
|
||||
j trap_unvectored_\MODE\()
|
||||
|
||||
ext_interrupt_\MODE\():
|
||||
li x5, 0x7EC
|
||||
sw x5, 0(x16)
|
||||
addi x6, x6, 4
|
||||
addi x16, x16, 4
|
||||
li x28, 0x10060000 // reset interrupt by clearing all the GPIO bits
|
||||
sw x0, 8(x28) // disable the first pin as an output
|
||||
sw x0, 40(x28) // write a 0 to the first output pin (reset interrupt)
|
||||
j trap_unvectored_\MODE\()
|
||||
|
||||
// Table of trap behavior
|
||||
// lists what to do on each exception (not interrupts)
|
||||
@ -244,29 +434,30 @@ accessfault:
|
||||
// Expected exceptions should increment the EPC to the next instruction and return
|
||||
|
||||
.align 2 // aligns this data table to an 4 byte boundary
|
||||
trap_handler_vector_table:
|
||||
.4byte segfault // 0: instruction address misaligned
|
||||
.4byte instrfault // 1: instruction access fault
|
||||
.4byte illegalinstr // 2: illegal instruction
|
||||
.4byte segfault // 3: breakpoint
|
||||
.4byte segfault // 4: load address misaligned
|
||||
.4byte accessfault // 5: load access fault
|
||||
.4byte segfault // 6: store address misaligned
|
||||
.4byte accessfault // 7: store access fault
|
||||
.4byte ecallhandler // 8: ecall from U-mode
|
||||
.4byte ecallhandler // 9: ecall from S-mode
|
||||
.4byte segfault // 10: reserved
|
||||
.4byte ecallhandler // 11: ecall from M-mode
|
||||
.4byte instrfault // 12: instruction page fault
|
||||
.4byte trapreturn // 13: load page fault
|
||||
.4byte segfault // 14: reserved
|
||||
.4byte trapreturn // 15: store page fault
|
||||
exception_vector_table_\MODE\():
|
||||
.4byte addr_misaligned_\MODE\() // 0: instruction address misaligned
|
||||
.4byte instrfault_\MODE\() // 1: instruction access fault
|
||||
.4byte illegalinstr_\MODE\() // 2: illegal instruction
|
||||
.4byte breakpt_\MODE\() // 3: breakpoint
|
||||
.4byte addr_misaligned_\MODE\() // 4: load address misaligned
|
||||
.4byte accessfault_\MODE\() // 5: load access fault
|
||||
.4byte addr_misaligned_\MODE\() // 6: store address misaligned
|
||||
.4byte accessfault_\MODE\() // 7: store access fault
|
||||
.4byte ecallhandler_\MODE\() // 8: ecall from U-mode
|
||||
.4byte ecallhandler_\MODE\() // 9: ecall from S-mode
|
||||
.4byte segfault_\MODE\() // 10: reserved
|
||||
.4byte ecallhandler_\MODE\() // 11: ecall from M-mode
|
||||
.4byte instrpagefault_\MODE\() // 12: instruction page fault
|
||||
.4byte trapreturn_\MODE\() // 13: load page fault
|
||||
.4byte segfault_\MODE\() // 14: reserved
|
||||
.4byte trapreturn_\MODE\() // 15: store page fault
|
||||
|
||||
.align 2
|
||||
trap_return_pagetype_table:
|
||||
trap_return_pagetype_table_\MODE\():
|
||||
.4byte 0xC // 0: kilopage has 12 offset bits
|
||||
.4byte 0x16 // 1: megapage has 22 offset bits
|
||||
|
||||
trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler and continue with the test
|
||||
.endm
|
||||
|
||||
// Test Summary table!
|
||||
@ -367,7 +558,7 @@ trap_return_pagetype_table:
|
||||
// they generally do not fault or cause issues as long as these modes are enabled
|
||||
// *** add functionality to check if modes are enabled before jumping? maybe cause a fault if not?
|
||||
|
||||
.macro GOTO_M_MODE RETURN_VPN RETURN_PAGETYPE
|
||||
.macro GOTO_M_MODE RETURN_VPN=0x0 RETURN_PAGETYPE=0x0
|
||||
li a0, 2 // determine trap handler behavior (go to machine mode)
|
||||
li a1, \RETURN_VPN // return VPN
|
||||
li a2, \RETURN_PAGETYPE // return page types
|
||||
@ -375,7 +566,7 @@ trap_return_pagetype_table:
|
||||
// now in S mode
|
||||
.endm
|
||||
|
||||
.macro GOTO_S_MODE RETURN_VPN RETURN_PAGETYPE
|
||||
.macro GOTO_S_MODE RETURN_VPN=0x0 RETURN_PAGETYPE=0x0
|
||||
li a0, 3 // determine trap handler behavior (go to supervisor mode)
|
||||
li a1, \RETURN_VPN // return VPN
|
||||
li a2, \RETURN_PAGETYPE // return page types
|
||||
@ -383,7 +574,7 @@ trap_return_pagetype_table:
|
||||
// now in S mode
|
||||
.endm
|
||||
|
||||
.macro GOTO_U_MODE RETURN_VPN RETURN_PAGETYPE
|
||||
.macro GOTO_U_MODE RETURN_VPN=0x0 RETURN_PAGETYPE=0x0
|
||||
li a0, 4 // determine trap handler behavior (go to user mode)
|
||||
li a1, \RETURN_VPN // return VPN
|
||||
li a2, \RETURN_PAGETYPE // return page types
|
||||
|
||||
@ -25,7 +25,7 @@
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
s_file_begin:
|
||||
TRAP_HANDLER m
|
||||
|
||||
// Test 5.2.3.1: testing Read-only access to Machine info CSRs
|
||||
CSR_R_ACCESS mvendorid
|
||||
|
||||
@ -25,7 +25,7 @@
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
s_file_begin:
|
||||
TRAP_HANDLER m
|
||||
// Test 5.3.2.2: Machine ISA register test
|
||||
|
||||
// Misa is a specific case *** so I don't want to add a whole test case for reading nonzero but unkown value CSRs.
|
||||
|
||||
@ -0,0 +1,45 @@
|
||||
///////////////////////////////////////////
|
||||
//
|
||||
// WALLY-unvectored-interrupt
|
||||
//
|
||||
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
|
||||
//
|
||||
// Created 2022-03-11
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
#include "WALLY-TEST-LIB-64.h"
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
// test 5.3.1.5 Unvectored interrupt tests
|
||||
|
||||
TRAP_HANDLER m, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits.
|
||||
|
||||
li x28, 0x8
|
||||
csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode
|
||||
WRITE_READ_CSR mie, 0xFFF // *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
|
||||
|
||||
// cause traps, ensuring that we DONT go through the vectored part of the trap handler
|
||||
// *** this assumes that interrupt code 0 remains reserved
|
||||
|
||||
CAUSE_TIME_INTERRUPT // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
|
||||
CAUSE_SOFT_INTERRUPT // *** exiting out of the trap handler after these is current;y broken
|
||||
CAUSE_EXT_INTERRUPT
|
||||
|
||||
END_TESTS
|
||||
|
||||
TEST_STACK_AND_DATA
|
||||
@ -25,7 +25,8 @@
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
s_file_begin:
|
||||
TRAP_HANDLER m
|
||||
|
||||
// Test 5.3.2.3: Scratch registers test
|
||||
|
||||
WRITE_READ_CSR mscratch, 0x111 // check that mscratch is readable and writeable in machine mode
|
||||
|
||||
@ -25,7 +25,7 @@
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
s_file_begin:
|
||||
TRAP_HANDLER m
|
||||
|
||||
// Test 5.3.2.3: Scratch registers test
|
||||
WRITE_READ_CSR sscratch, 0x111 // check that sscratch is readable and writeable in machine mode
|
||||
|
||||
@ -0,0 +1,55 @@
|
||||
///////////////////////////////////////////
|
||||
//
|
||||
// WALLY-unvectored-interrupt
|
||||
//
|
||||
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
|
||||
//
|
||||
// Created 2022-03-11
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
#include "WALLY-TEST-LIB-64.h"
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
// test 5.3.1.5 Unvectored interrupt tests
|
||||
|
||||
TRAP_HANDLER s, VECTORED=0, DEBUG=1 // turn off vectored interrupts, while turning on recording of mstatus bits.
|
||||
|
||||
// li x28, 0x8
|
||||
// csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode
|
||||
// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
|
||||
|
||||
WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
|
||||
|
||||
GOTO_S_MODE
|
||||
|
||||
// cause traps, ensuring that we DONT go through the vectored part of the trap handler
|
||||
// *** this assumes that interrupt code 0 remains reserved
|
||||
|
||||
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
|
||||
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
|
||||
// CAUSE_EXT_INTERRUPT
|
||||
|
||||
GOTO_U_MODE
|
||||
|
||||
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
|
||||
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
|
||||
// CAUSE_EXT_INTERRUPT
|
||||
|
||||
END_TESTS
|
||||
|
||||
TEST_STACK_AND_DATA
|
||||
@ -0,0 +1,76 @@
|
||||
///////////////////////////////////////////
|
||||
//
|
||||
// WALLY-trap
|
||||
//
|
||||
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
|
||||
//
|
||||
// Created 2022-02-20
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
#include "WALLY-TEST-LIB-64.h"
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
CAUSE_TRAP_TRIGGERS // initialize code that will cause traps for consistent mtval addresses
|
||||
|
||||
TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
|
||||
|
||||
li x28, 0x8
|
||||
csrs mstatus, x28 // set mstatus.MIE bit to 1
|
||||
WRITE_READ_CSR mie, 0xFFF // Enable interrupts from all sources // *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
|
||||
|
||||
// test 5.3.1.4 Basic trap tests
|
||||
|
||||
// jal cause_instr_addr_misaligned //skipped becuase this exception may be impossible when compressed instructions are enabled)
|
||||
jal cause_instr_access
|
||||
jal cause_illegal_instr
|
||||
jal cause_breakpnt
|
||||
jal cause_load_addr_misaligned
|
||||
jal cause_load_acc
|
||||
jal cause_store_addr_misaligned
|
||||
jal cause_store_acc
|
||||
GOTO_U_MODE // Causes M mode ecall
|
||||
GOTO_S_MODE // Causes U mode ecall
|
||||
GOTO_M_MODE // Causes S mode ecall
|
||||
|
||||
jal cause_time_interrupt // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
|
||||
jal cause_soft_interrupt // *** exiting out of the trap handler after these is current;y broken
|
||||
jal cause_ext_interrupt
|
||||
|
||||
// try the traps again with mideleg = medeleg = all 1's to ensure traps still go to M mode from M mode
|
||||
|
||||
WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF
|
||||
WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
|
||||
|
||||
// jal cause_instr_addr_misaligned //skipped becuase this exception may be impossible when compressed instructions are enabled)
|
||||
jal cause_instr_access
|
||||
jal cause_illegal_instr
|
||||
jal cause_breakpnt
|
||||
jal cause_load_addr_misaligned
|
||||
jal cause_load_acc
|
||||
jal cause_store_addr_misaligned
|
||||
jal cause_store_acc
|
||||
jal cause_ecall // M mode ecall
|
||||
|
||||
jal cause_time_interrupt // *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
|
||||
jal cause_soft_interrupt // *** exiting out of the trap handler after these is current;y broken
|
||||
jal cause_ext_interrupt
|
||||
|
||||
END_TESTS
|
||||
|
||||
TEST_STACK_AND_DATA
|
||||
|
||||
@ -0,0 +1,85 @@
|
||||
///////////////////////////////////////////
|
||||
//
|
||||
// WALLY-trap-s
|
||||
//
|
||||
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
|
||||
//
|
||||
// Created 2022-03-11
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
#include "WALLY-TEST-LIB-64.h"
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
// test 5.3.1.4 Basic trap tests
|
||||
|
||||
TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
|
||||
TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well
|
||||
|
||||
// Like WALLY-trap, cause all the same traps from S mode and make sure they go to machine mode with zeroed mideleg, medeleg
|
||||
|
||||
GOTO_S_MODE
|
||||
|
||||
li x28, 0x8
|
||||
csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode
|
||||
// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
|
||||
|
||||
|
||||
// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled)
|
||||
CAUSE_INSTR_ACCESS
|
||||
CAUSE_ILLEGAL_INSTR
|
||||
CAUSE_BREAKPNT
|
||||
CAUSE_LOAD_ADDR_MISALIGNED
|
||||
CAUSE_LOAD_ACC
|
||||
CAUSE_STORE_ADDR_MISALIGNED
|
||||
CAUSE_STORE_ACC
|
||||
CAUSE_ECALL
|
||||
|
||||
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
|
||||
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
|
||||
// CAUSE_EXT_INTERRUPT
|
||||
|
||||
|
||||
// Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler
|
||||
// We can tell which one becuase the different trap handler modes write different bits of the status register
|
||||
// to the output when debug is on.
|
||||
|
||||
GOTO_M_MODE // so we can write the delegate registers
|
||||
|
||||
WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF
|
||||
WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
|
||||
|
||||
GOTO_S_MODE
|
||||
|
||||
// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled)
|
||||
CAUSE_INSTR_ACCESS
|
||||
CAUSE_ILLEGAL_INSTR
|
||||
CAUSE_BREAKPNT
|
||||
CAUSE_LOAD_ADDR_MISALIGNED
|
||||
CAUSE_LOAD_ACC
|
||||
CAUSE_STORE_ADDR_MISALIGNED
|
||||
CAUSE_STORE_ACC
|
||||
CAUSE_ECALL
|
||||
|
||||
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
|
||||
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
|
||||
// CAUSE_EXT_INTERRUPT
|
||||
|
||||
END_TESTS
|
||||
|
||||
TEST_STACK_AND_DATA
|
||||
|
||||
@ -0,0 +1,84 @@
|
||||
///////////////////////////////////////////
|
||||
//
|
||||
// WALLY-trap-u
|
||||
//
|
||||
// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
|
||||
//
|
||||
// Created 2022-03-11
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
|
||||
#include "WALLY-TEST-LIB-64.h"
|
||||
|
||||
INIT_TESTS
|
||||
|
||||
// test 5.3.1.4 Basic trap tests
|
||||
|
||||
TRAP_HANDLER m, DEBUG=1 // turn on recording mtval and status bits on traps
|
||||
TRAP_HANDLER s, DEBUG=1 // have S mode trap handler as well
|
||||
|
||||
// Like WALLY-trap, cause all the same traps from U mode and make sure they go to machine mode with zeroed mideleg, medeleg
|
||||
|
||||
GOTO_U_MODE
|
||||
|
||||
// li x28, 0x8
|
||||
// csrs sstatus, x28 // set sstatus.MIE bit to 1 // *** might be unneccessary for s mode
|
||||
// WRITE_READ_CSR mie, 0xFFFF *** commented out until I can get the trap handler (and spike for time interrupts) to work correctly with interrupts
|
||||
|
||||
|
||||
// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled)
|
||||
CAUSE_INSTR_ACCESS
|
||||
CAUSE_ILLEGAL_INSTR
|
||||
CAUSE_BREAKPNT
|
||||
CAUSE_LOAD_ADDR_MISALIGNED
|
||||
CAUSE_LOAD_ACC
|
||||
CAUSE_STORE_ADDR_MISALIGNED
|
||||
CAUSE_STORE_ACC
|
||||
CAUSE_ECALL
|
||||
|
||||
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
|
||||
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
|
||||
// CAUSE_EXT_INTERRUPT
|
||||
|
||||
|
||||
// Now delegate all traps to S mode and attempt them again, ensuring they now go to the S mode trap handler
|
||||
// We can tell which one becuase the different trap handler modes write different bits of the status register
|
||||
// to the output when debug is on.
|
||||
|
||||
GOTO_M_MODE // so we can write the delegate registers
|
||||
|
||||
WRITE_READ_CSR medeleg, 0xFFFFFFFFFFFFFFFF
|
||||
WRITE_READ_CSR mideleg, 0xFFFFFFFFFFFFFFFF
|
||||
|
||||
GOTO_U_MODE
|
||||
|
||||
// CAUSE_INSTR_ADDR_MISALIGNED //skipped becuase this exception may be impossible when compressed instructions are enabled)
|
||||
CAUSE_INSTR_ACCESS
|
||||
CAUSE_ILLEGAL_INSTR
|
||||
CAUSE_BREAKPNT
|
||||
CAUSE_LOAD_ADDR_MISALIGNED
|
||||
CAUSE_LOAD_ACC
|
||||
CAUSE_STORE_ADDR_MISALIGNED
|
||||
CAUSE_STORE_ACC
|
||||
CAUSE_ECALL
|
||||
|
||||
// CAUSE_TIME_INTERRUPT *** intentionally causing this trap seems difficult in spike. although it is possible for it to accidentally happen.
|
||||
// CAUSE_SOFT_INTERRUPT *** exiting out of the trap handler after these is current;y broken
|
||||
// CAUSE_EXT_INTERRUPT
|
||||
|
||||
END_TESTS
|
||||
|
||||
TEST_STACK_AND_DATA
|
||||
@ -430,3 +430,67 @@ FFFFFF33
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
04BEEF1B
|
||||
00000009
|
||||
80000000
|
||||
0000000A
|
||||
00000004
|
||||
00000061
|
||||
00000061
|
||||
00000065
|
||||
00000060
|
||||
00000001
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
04BEEF1C
|
||||
00000009
|
||||
80000000
|
||||
00000003
|
||||
00080000
|
||||
00080000
|
||||
00080000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00080000
|
||||
00080000
|
||||
FFFFFFFF
|
||||
FFF7FFFF
|
||||
00000000
|
||||
00000000
|
||||
04BEEF1D
|
||||
00000009
|
||||
80000000
|
||||
00000003
|
||||
00000001
|
||||
00000001
|
||||
00000001
|
||||
00000000
|
||||
00080000
|
||||
00000000
|
||||
00080001
|
||||
00000001
|
||||
FFFFFFFF
|
||||
FFFFFFFE
|
||||
00000000
|
||||
00000000
|
||||
04BEEF1E
|
||||
00000009
|
||||
80000000
|
||||
0000000A
|
||||
00000004
|
||||
00000061
|
||||
00000061
|
||||
0000006e
|
||||
00000060
|
||||
00000001
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
|
||||
@ -41,11 +41,12 @@ trap_handler: #####
|
||||
###################
|
||||
###################
|
||||
# save registers
|
||||
addi sp, sp, 0x20
|
||||
addi sp, sp, 0x28
|
||||
sw t0, 0x00(sp)
|
||||
sw t1, 0x08(sp)
|
||||
sw t2, 0x10(sp)
|
||||
sw t3, 0x18(sp)
|
||||
sw t4, 0x20(sp)
|
||||
|
||||
# ===================================
|
||||
# ===== Signature Output Format =====
|
||||
@ -56,7 +57,7 @@ trap_handler: #####
|
||||
#
|
||||
# <offset>: <contents>
|
||||
# 0x00: test ID = 0x<group_num>BEEF<intr_num>
|
||||
# 0x04: mcause (low) = 0x0000000B
|
||||
# 0x04: mcause (low) = 0x0000000B (MEIP) or 0x00000009 (SEIP)
|
||||
# 0x08: mcause (high) = 0x80000000
|
||||
# ----- If GPIO -----
|
||||
# 0x0C: claim ID = 3
|
||||
@ -87,18 +88,26 @@ trap_handler: #####
|
||||
add t0, t0, a1
|
||||
sw t0, 0x00(s0)
|
||||
|
||||
# 0x04: mcause (low) = 0x0000000B
|
||||
# 0x04: mcause (low) = 0x0000000B (MEIP) or 0x00000009 (SEIP)
|
||||
# 0x08: mcause (high) = 0x80000000
|
||||
# Expect interrupt from src 11 (machine external interrupt)
|
||||
csrrc t1, mcause, x0
|
||||
sw t1, 0x04(s0)
|
||||
srli t1,t1,32
|
||||
sw t1, 0x08(s0)
|
||||
csrrc t0, mcause, x0
|
||||
andi t1, t0, 0x7FF
|
||||
sw t0, 0x04(s0)
|
||||
srli t0,t0,32
|
||||
sw t0, 0x08(s0)
|
||||
# MEIP or SEIP?
|
||||
# MEIP is on context 0
|
||||
li t4, 0x0C200004
|
||||
li t0, 0xB
|
||||
beq t1, t0, meip
|
||||
# SEIP is on context 1
|
||||
li t4, 0x0C201004
|
||||
meip:
|
||||
|
||||
# 0x: claim ID
|
||||
# 0x0C: claim ID
|
||||
# 3: GPIO
|
||||
# A: UART
|
||||
li t0, 0x0C200004
|
||||
mv t0, t4
|
||||
lw t1, 0(t0)
|
||||
sw t1, 0x0C(s0)
|
||||
li t2, 0xA
|
||||
@ -150,7 +159,7 @@ trap_handler: #####
|
||||
# signal to main code that gpio was serviced
|
||||
ori a0, a0, 0b00001000
|
||||
# signal to plic that gpio was serviced
|
||||
li t0, 0x0C200004
|
||||
mv t0, t4
|
||||
li t1, 3
|
||||
sw t1, 0(t0)
|
||||
j trap_handler_end
|
||||
@ -181,7 +190,7 @@ trap_handler: #####
|
||||
# signal to main code that uart was serviced
|
||||
ori a0, a0, 0b00010000
|
||||
# signal to plic that uart was serviced
|
||||
li t0, 0x0C200004
|
||||
mv t0, t4
|
||||
li t1, 0xA
|
||||
sw t1, 0(t0)
|
||||
|
||||
@ -193,7 +202,8 @@ trap_handler: #####
|
||||
ld t1, 0x08(sp)
|
||||
ld t2, 0x10(sp)
|
||||
ld t3, 0x18(sp)
|
||||
addi sp, sp, SEXT_IMM(-0x20)
|
||||
ld t4, 0x20(sp)
|
||||
addi sp, sp, SEXT_IMM(-0x28)
|
||||
mret
|
||||
|
||||
################
|
||||
@ -267,7 +277,7 @@ main_code: #####
|
||||
# set MEIE
|
||||
li t0, 0x800
|
||||
csrrs x0, mie, t0
|
||||
Intr01BEEF01:
|
||||
Intr01BEEF00:
|
||||
# UART TX 'h'
|
||||
li t0, 0x10000000
|
||||
li t1, 'h'
|
||||
@ -276,7 +286,7 @@ Intr01BEEF01:
|
||||
li t1, 0b00010000
|
||||
1: bne t1,a0,1b
|
||||
li a0, 0
|
||||
Intr01BEEF02:
|
||||
Intr01BEEF01:
|
||||
# GPIO raise pin 19
|
||||
li t0, 0x10060000
|
||||
li t1, 0x00080000
|
||||
@ -286,12 +296,12 @@ Intr01BEEF02:
|
||||
1: bne t1,a0,1b
|
||||
li a0, 0
|
||||
# Now let's go bonkers and trigger both!
|
||||
Intr01BEEF03:
|
||||
Intr01BEEF02:
|
||||
# TX 'e'
|
||||
li t0, 0x10000000
|
||||
li t1, 'e'
|
||||
sb t1, 0(t0)
|
||||
Intr01BEEF04:
|
||||
Intr01BEEF03:
|
||||
# GPIO lower pin 19 raise pin 0
|
||||
li t0, 0x10060000
|
||||
li t1, 0x00000001
|
||||
@ -787,6 +797,91 @@ Intr03BEEF1A:
|
||||
li t1, 0b00010000
|
||||
1: bne t1,a0,1b
|
||||
li a0, 0
|
||||
|
||||
####################################################
|
||||
##### Test 4 - Signs of Life on PLIC Context 1 #####
|
||||
####################################################
|
||||
li a1, 0x04beef00 # group ID
|
||||
# clear MEIE (good to turn off while configuring peripherals)
|
||||
li t0, 0x800
|
||||
csrrc x0, mie, t0
|
||||
# ========== Configure PLIC ==========
|
||||
# priority threshold = 0
|
||||
li t0, 0xC200000
|
||||
li t1, 0
|
||||
sw t1, 0(t0)
|
||||
# source 3 (GPIO) priority = 6
|
||||
li t0, 0xC000000
|
||||
li t1, 6
|
||||
sw t1, 0x0C(t0)
|
||||
# source 0xA (UART) priority = 7
|
||||
li t1, 7
|
||||
sw t1, 0x28(t0)
|
||||
# disable sources 3,0xA on context 0
|
||||
li t0, 0x0C002000
|
||||
li t1, 0
|
||||
sw t1, 0(t0)
|
||||
# enable sources 3,0xA on context 1
|
||||
li t0, 0x0C002080
|
||||
li t1, 0b10000001000
|
||||
sw t1, 0(t0)
|
||||
# ========== Configure UART ==========
|
||||
# MCR: Loop = 1
|
||||
li t0, 0x10000000
|
||||
li t1, 0b10000
|
||||
sb t1, 4(t0)
|
||||
# LCR: Use 8 data bits plus odd parity bit
|
||||
li t1, 0b00001011
|
||||
sb t1, 3(t0)
|
||||
# IER: Enable Received Data Available Interrupt
|
||||
li t1, 0x01
|
||||
sb t1, 1(t0)
|
||||
# ========== Configure GPIO ==========
|
||||
# raise all input_en
|
||||
li t0, 0x10060000
|
||||
li t1, 0xFFFFFFFF
|
||||
sw t1, 0x04(t0)
|
||||
# raise all output_en
|
||||
sw t1, 0x08(t0)
|
||||
# raise all input_en
|
||||
sw t1, 0x18(t0)
|
||||
# ========== Execute Test ==========
|
||||
# set MEIE and SEIE
|
||||
li t0, 0xA00
|
||||
csrrs x0, mie, t0
|
||||
Intr04BEEF1B:
|
||||
# UART TX 'e'
|
||||
li t0, 0x10000000
|
||||
li t1, 'e'
|
||||
sb t1, 0(t0)
|
||||
# wait to finish
|
||||
li t1, 0b00010000
|
||||
1: bne t1,a0,1b
|
||||
li a0, 0
|
||||
Intr04BEEF1C:
|
||||
# GPIO raise pin 19
|
||||
li t0, 0x10060000
|
||||
li t1, 0x00080000
|
||||
sw t1, 0x0C(t0)
|
||||
# wait to finish
|
||||
li t1, 0b00001000
|
||||
1: bne t1,a0,1b
|
||||
li a0, 0
|
||||
# Now let's go bonkers and trigger both!
|
||||
Intr04BEEF1D:
|
||||
# TX 'n'
|
||||
li t0, 0x10000000
|
||||
li t1, 'n'
|
||||
sb t1, 0(t0)
|
||||
Intr04BEEF1E:
|
||||
# GPIO lower pin 19 raise pin 0
|
||||
li t0, 0x10060000
|
||||
li t1, 0x00000001
|
||||
sw t1, 0x0C(t0)
|
||||
# wait to finish
|
||||
li t1, 0b00011000
|
||||
1: bne t1,a0,1b
|
||||
li a0, 0
|
||||
# ---------------------------------------------------------------------------------------------
|
||||
|
||||
//terminate_test:
|
||||
|
||||
@ -117,7 +117,7 @@ cause_ecall:
|
||||
cause_time_interrupt:
|
||||
// The following code works for both RV32 and RV64.
|
||||
// RV64 alone would be easier using double-word adds and stores
|
||||
li x28, 0x100 // Desired offset from the present time
|
||||
li x28, 0x30 // Desired offset from the present time
|
||||
la x29, 0x02004000 // MTIMECMP register in CLINT
|
||||
la x30, 0x0200BFF8 // MTIME register in CLINT
|
||||
lw x7, 0(x30) // low word of MTIME
|
||||
@ -158,9 +158,7 @@ end_trap_triggers:
|
||||
|
||||
// Set up the exception Handler, keeping the original handler in x4.
|
||||
la x1, trap_handler_\MODE\()
|
||||
.if (\VECTORED\() == 1)
|
||||
ori x1, x1, 0x1 // set mode field of tvec to 1, forcing vectored interrupts
|
||||
.endif
|
||||
ori x1, x1, \VECTORED // set mode field of tvec to VECTORED, which will force vectored interrupts if it's 1.
|
||||
|
||||
.if (\MODE\() == m)
|
||||
csrrw x4, \MODE\()tvec, x1 // x4 reserved for "default" trap handler address that needs to be restored before halting this test.
|
||||
@ -172,6 +170,10 @@ end_trap_triggers:
|
||||
li a1, 0
|
||||
li a2, 0 // reset trap handler inputs to zero
|
||||
|
||||
la x29, 0x02004000 // MTIMECMP register in CLINT
|
||||
li x30, 0xFFFFFFFF
|
||||
sd x30, 0(x29) // set mtimecmp to 0xFFFFFFFF to really make sure time interrupts don't go off immediately after being enabled
|
||||
|
||||
j trap_handler_end_\MODE\() // skip the trap handler when it is being defined.
|
||||
|
||||
// ---------------------------------------------------------------------------------------------
|
||||
@ -214,17 +216,17 @@ trap_handler_\MODE\():
|
||||
// *** ASSUMES that a cause value of 0 for an interrupt is unimplemented
|
||||
// otherwise, a vectored interrupt handler should jump to trap_handler_\MODE\() + 4 * Interrupt cause code
|
||||
// No matter the value of VECTORED, exceptions (not interrupts) are handled in an unvecotred way
|
||||
j s_soft_interrupt_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
|
||||
j soft_interrupt_\MODE\() // 1: instruction access fault // the zero spot is taken up by the instruction to skip this table.
|
||||
j segfault_\MODE\() // 2: reserved
|
||||
j m_soft_interrupt_\MODE\() // 3: breakpoint
|
||||
j soft_interrupt_\MODE\() // 3: breakpoint
|
||||
j segfault_\MODE\() // 4: reserved
|
||||
j s_time_interrupt_\MODE\() // 5: load access fault
|
||||
j time_interrupt_\MODE\() // 5: load access fault
|
||||
j segfault_\MODE\() // 6: reserved
|
||||
j m_time_interrupt_\MODE\() // 7: store access fault
|
||||
j time_interrupt_\MODE\() // 7: store access fault
|
||||
j segfault_\MODE\() // 8: reserved
|
||||
j s_ext_interrupt_\MODE\() // 9: ecall from S-mode
|
||||
j ext_interrupt_\MODE\() // 9: ecall from S-mode
|
||||
j segfault_\MODE\() // 10: reserved
|
||||
j m_ext_interrupt_\MODE\() // 11: ecall from M-mode
|
||||
j ext_interrupt_\MODE\() // 11: ecall from M-mode
|
||||
// 12 through >=16 are reserved or designated for platform use
|
||||
|
||||
trap_unvectored_\MODE\():
|
||||
@ -245,12 +247,11 @@ trap_unvectored_\MODE\():
|
||||
addi x16, x16, 8
|
||||
|
||||
csrr x1, \MODE\()status
|
||||
.if (\MODE\() == m) // Taking traps in different modes means we want to get different bits from the status register.
|
||||
li x5, 0x1888 // mask bits to select MPP, MPIE, and MIE.
|
||||
.else
|
||||
li x5, 0x122 // mask bits to select SPP, SPIE, and SIE.
|
||||
.endif
|
||||
|
||||
.if (\MODE\() == m) // Taking traps in different modes means we want to get different bits from the status register.
|
||||
li x5, 0x1888 // mask bits to select MPP, MPIE, and MIE.
|
||||
.else
|
||||
li x5, 0x122 // mask bits to select SPP, SPIE, and SIE.
|
||||
.endif
|
||||
and x5, x5, x1
|
||||
sd x5, 0(x16) // store masked out status bits to the output
|
||||
addi x6, x6, 8
|
||||
@ -265,7 +266,6 @@ trap_unvectored_\MODE\():
|
||||
and x5, x5, x1
|
||||
bnez x5, trapreturn_\MODE\() // return from interrupt
|
||||
// Other trap handling is specified in the vector Table
|
||||
csrr x1, \MODE\()cause
|
||||
slli x1, x1, 3 // multiply cause by 8 to get offset in vector Table
|
||||
la x5, exception_vector_table_\MODE\()
|
||||
add x5, x5, x1 // compute address of vector in Table
|
||||
@ -345,7 +345,7 @@ trapreturn_finished_\MODE\():
|
||||
csrw \MODE\()epc, x1 // update the epc with address of next instruction
|
||||
ld x5, -16(sp) // restore registers from stack before returning
|
||||
ld x1, -8(sp)
|
||||
csrw \MODE\()ip, 0x0 // clear interrupt pending register to indicate interrupt has been handled
|
||||
// *** this should be handled by indirectly clearing this bit csrw \MODE\()ip, 0x0 // clear interrupt pending register to indicate interrupt has been handled
|
||||
\MODE\()ret // return from trap
|
||||
|
||||
ecallhandler_\MODE\():
|
||||
@ -376,7 +376,7 @@ ecallhandler_changetosupervisormode_\MODE\():
|
||||
ecallhandler_changetousermode_\MODE\():
|
||||
// Force mstatus.MPP (bits 12:11) to 00 to enter user mode after mret
|
||||
li x1, 0b1100000000000
|
||||
csrc mstatus, x1
|
||||
csrc \MODE\()status, x1
|
||||
j trapreturn_\MODE\()
|
||||
|
||||
instrpagefault_\MODE\():
|
||||
@ -400,7 +400,7 @@ addr_misaligned_\MODE\():
|
||||
breakpt_\MODE\():
|
||||
j trapreturn_\MODE\()
|
||||
|
||||
s_soft_interrupt_\MODE\(): // these labels are here to make sure the code compiles, but don't actually do anything yet
|
||||
soft_interrupt_\MODE\():
|
||||
li x5, 0x7EC // write 0x7EC (looks like VEC) to the output before the mcause and extras to indicate that this trap was handled with a vector table.
|
||||
sd x5, 0(x16)
|
||||
addi x6, x6, 8
|
||||
@ -409,30 +409,19 @@ s_soft_interrupt_\MODE\(): // these labels are here to make sure the code compil
|
||||
sw x0, 0(x28)
|
||||
j trap_unvectored_\MODE\()
|
||||
|
||||
m_soft_interrupt_\MODE\():
|
||||
time_interrupt_\MODE\():
|
||||
li x5, 0x7EC
|
||||
sd x5, 0(x16)
|
||||
addi x6, x6, 8
|
||||
addi x16, x16, 8
|
||||
la x28, 0x02000000 // Reset by clearing MSIP interrupt from CLINT
|
||||
sw x0, 0(x28)
|
||||
|
||||
la x29, 0x02004000 // MTIMECMP register in CLINT
|
||||
li x30, 0xFFFFFFFF
|
||||
sd x30, 0(x29) // reset interrupt by setting mtimecmp to 0xFFFFFFFF
|
||||
|
||||
j trap_unvectored_\MODE\()
|
||||
|
||||
s_time_interrupt_\MODE\():
|
||||
li x5, 0x7EC
|
||||
sd x5, 0(x16)
|
||||
addi x6, x6, 8
|
||||
addi x16, x16, 8
|
||||
j trap_unvectored_\MODE\()
|
||||
|
||||
m_time_interrupt_\MODE\():
|
||||
li x5, 0x7EC
|
||||
sd x5, 0(x16)
|
||||
addi x6, x6, 8
|
||||
addi x16, x16, 8
|
||||
j trap_unvectored_\MODE\()
|
||||
|
||||
s_ext_interrupt_\MODE\():
|
||||
ext_interrupt_\MODE\():
|
||||
li x5, 0x7EC
|
||||
sd x5, 0(x16)
|
||||
addi x6, x6, 8
|
||||
@ -442,17 +431,6 @@ s_ext_interrupt_\MODE\():
|
||||
sw x0, 40(x28) // write a 0 to the first output pin (reset interrupt)
|
||||
j trap_unvectored_\MODE\()
|
||||
|
||||
m_ext_interrupt_\MODE\():
|
||||
li x5, 0x7EC
|
||||
sd x5, 0(x16)
|
||||
addi x6, x6, 8
|
||||
addi x16, x16, 8
|
||||
li x28, 0x10060000 // reset interrupt by clearing all the GPIO bits
|
||||
sw x0, 8(x28) // disable the first pin as an output
|
||||
sw x0, 40(x28) // write a 0 to the first output pin (reset interrupt)
|
||||
j trap_unvectored_\MODE\()
|
||||
|
||||
|
||||
// Table of trap behavior
|
||||
// lists what to do on each exception (not interrupts)
|
||||
// unexpected exceptions should cause segfaults for easy detection
|
||||
@ -720,87 +698,6 @@ trap_handler_end_\MODE\(): // place to jump to so we can skip the trap handler a
|
||||
addi x16, x16, 8
|
||||
.endm
|
||||
|
||||
// // The following tests involve causing many of the interrupts and exceptions that are easily done in a few lines
|
||||
// // This effectively includes everything that isn't to do with page faults (virtual memory)
|
||||
|
||||
// .macro CAUSE_INSTR_ADDR_MISALIGNED
|
||||
// // cause a misaligned address trap
|
||||
// auipc x28, 0 // get current PC, which is aligned
|
||||
// addi x28, x28, 0x1 // add 1 to pc to create misaligned address
|
||||
// jalr x28 // cause instruction address midaligned trap
|
||||
// .endm
|
||||
|
||||
// .macro CAUSE_INSTR_ACCESS
|
||||
// la x28, 0x0 // address zero is an address with no memory
|
||||
// jalr x28 // cause instruction access trap
|
||||
// .endm
|
||||
|
||||
// .macro CAUSE_ILLEGAL_INSTR
|
||||
// .word 0x00000000 // a 32 bit zros is an illegal instruction
|
||||
// .endm
|
||||
|
||||
// .macro CAUSE_BREAKPNT // ****
|
||||
// ebreak
|
||||
// .endm
|
||||
|
||||
// .macro CAUSE_LOAD_ADDR_MISALIGNED
|
||||
// auipc x28, 0 // get current PC, which is aligned
|
||||
// addi x28, x28, 1
|
||||
// lw x29, 0(x28) // load from a misaligned address
|
||||
// .endm
|
||||
|
||||
// .macro CAUSE_LOAD_ACC
|
||||
// la x28, 0 // 0 is an address with no memory
|
||||
// lw x29, 0(x28) // load from unimplemented address
|
||||
// .endm
|
||||
|
||||
// .macro CAUSE_STORE_ADDR_MISALIGNED
|
||||
// auipc x28, 0 // get current PC, which is aligned
|
||||
// addi x28, x28, 1
|
||||
// sw x29, 0(x28) // store to a misaligned address
|
||||
// .endm
|
||||
|
||||
// .macro CAUSE_STORE_ACC
|
||||
// la x28, 0 // 0 is an address with no memory
|
||||
// sw x29, 0(x28) // store to unimplemented address
|
||||
// .endm
|
||||
|
||||
// .macro CAUSE_ECALL
|
||||
// // *** ASSUMES you have already gone to the mode you need to call this from.
|
||||
// ecall
|
||||
// .endm
|
||||
|
||||
// .macro CAUSE_TIME_INTERRUPT
|
||||
// // The following code works for both RV32 and RV64.
|
||||
// // RV64 alone would be easier using double-word adds and stores
|
||||
// li x28, 0x100 // Desired offset from the present time
|
||||
// la x29, 0x02004000 // MTIMECMP register in CLINT
|
||||
// la x30, 0x0200BFF8 // MTIME register in CLINT
|
||||
// lw x7, 0(x30) // low word of MTIME
|
||||
// lw x31, 4(x30) // high word of MTIME
|
||||
// add x28, x7, x28 // add desired offset to the current time
|
||||
// bgtu x28, x7, nowrap // check new time exceeds current time (no wraparound)
|
||||
// addi x31, x31, 1 // if wrap, increment most significant word
|
||||
// sw x31,4(x29) // store into most significant word of MTIMECMP
|
||||
// nowrap:
|
||||
// sw x28, 0(x29) // store into least significant word of MTIMECMP
|
||||
// loop: j loop // wait until interrupt occurs
|
||||
// .endm
|
||||
|
||||
// .macro CAUSE_SOFT_INTERRUPT
|
||||
// la x28, 0x02000000 // MSIP register in CLINT
|
||||
// li x29, 1 // 1 in the lsb
|
||||
// sw x29, 0(x28) // Write MSIP bit
|
||||
// .endm
|
||||
|
||||
// .macro CAUSE_EXT_INTERRUPT
|
||||
// li x28, 0x10060000 // load base GPIO memory location
|
||||
// li x29, 0x1
|
||||
// sw x29, 8(x28) // enable the first pin as an output
|
||||
// sw x29, 28(x28) // set first pin to high interrupt enable
|
||||
// sw x29, 40(x28) // write a 1 to the first output pin (cause interrupt)
|
||||
// .endm
|
||||
|
||||
.macro END_TESTS
|
||||
// invokes one final ecall to return to machine mode then terminates this program, so the output is
|
||||
// 0x8: termination called from U mode
|
||||
|
||||
Loading…
Reference in New Issue
Block a user