Github_Repos/cvw
1
0
Fork 1
mirror of https://github.com/openhwgroup/cvw synced 2025-02-11 06:05:49 +00:00
Code Issues Packages Projects Releases Wiki Activity
3,360 Commits 5 Branches 2 Tags 53 MiB
c4618d1e57
Commit Graph

35 Commits

Author SHA1 Message Date
mmasserfrye
2675c217e0 cleaned lint for ppa.sv 2022-05-12 20:20:05 +00:00
David Harris
8372bc86a7 Removing unused signals 2022-05-12 14:36:15 +00:00
mmasserfrye
52b0e7d567 filled in ppa.sv, madzscript.py now synthesizes in parallel in puts results in csv 2022-05-12 07:22:06 +00:00
Ross Thompson
4d3fde3829 Updated wally to point to riscv-arch-test tag 2.7.3 2022-04-16 15:32:43 -05:00
Katherine Parry
c307cff503 fixed errors and warnings in rv32e 2022-04-07 17:21:20 +00:00
David Harris
049c55769a fpu compare simplification, minor cleanup 2022-03-29 17:11:28 +00:00
Katherine Parry
2042374102 FMA parameterized and FMA testbench reworked 2022-03-19 19:39:03 +00:00
David Harris
eda60a7691 Moved Softfloat / TestFloat 2022-02-26 19:17:32 +00:00
James Stine
b9480a4643 Added the 12T submodule to the project. 2022-02-03 19:26:41 -06:00
David Harris
069f270d1a Removed soc_flow 2022-01-31 22:58:33 +00:00
David Harris
2d112698b7 Replaced || and && with | and & 2022-01-31 01:07:35 +00:00
David Harris
c367d19fc6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-31 00:59:49 +00:00
David Harris
ea85e185f1 gitmodules 2022-01-31 00:59:44 +00:00
James Stine
ef811c7786 Remove book_flow to add back later - will add synthDC back within 30m 2022-01-28 08:18:30 -06:00
David Harris
384cd0d092 Added synthesis submodules 2022-01-27 14:31:34 +00:00
David Harris
1e533cdf25 Removed and restored embench-iot 2022-01-25 22:12:28 +00:00
David Harris
26013a984b Fixed sumtest reference output; added embench benchmark directory 2022-01-24 23:21:09 +00:00
David Harris
de7b9c127e Added E extension, and downloaded riscv-dv and embench-iot to addins 2022-01-17 14:42:59 +00:00
David Harris
e25760d8e5 Added C test cases 2022-01-11 21:01:48 +00:00
David Harris
27c1d73cb1 Code cleanup 2022-01-07 04:07:04 +00:00
Katherine Parry
631d05dcdc some FPU test fixes 2022-01-06 23:03:20 +00:00
David Harris
57d32e58c6 Switched riscv-arch-test to current hash 2021-12-29 18:52:52 +00:00
David Harris
c3bfa53db0 Added partially working MMU tests 2021-12-29 03:14:16 +00:00
David Harris
e97e512da9 Started FIR test code and started incorporating Imperas tests 2021-12-25 22:39:51 +00:00
David Harris
434f49c03e Removed riscv-isa-sim submodule from Wally; use it in /opt/riscv instead 2021-12-21 02:35:41 +00:00
David Harris
7a8162497b Added irscv-arch-test and rsicv-isa-sim 2021-12-15 12:38:35 -08:00
Ross Thompson
f061a26411 Cleaned up fpga synthesis script. 2021-12-13 18:26:54 -06:00
David Harris
74cf0eb96a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-13 07:57:49 -08:00
kwan
5ede8126fd priviledge .* removed, passed regression 2021-12-13 00:34:43 -08:00
David Harris
5d4014d351 Refactoring ALU and datapath muxes 2021-12-08 12:33:53 -08:00
Katherine Parry
d0e708f239 FMA uses one LOA 2021-12-07 14:15:43 -08:00
kwan
2a77bc8053 .* in ifu/ifu.sv eliminated 2021-12-02 09:45:55 -08:00
David Harris
e4861e11d1 Added coremark scripts to regression directory 2021-12-01 09:08:06 -08:00
Kevin Kim
869cd44533 added arch-test submodule 2021-11-30 18:22:08 -08:00
Kevin Kim
6323609da9 Added git submodules 
-riscv-arch-test
-rscv-isa-sim
submodules are added in addins/ directory
 2021-11-30 18:16:37 -08:00