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Author SHA1 Message Date
Ross Thompson
a0ee2f3d99 Removed redundant signals from cache. 2022-02-11 22:23:47 -06:00
Ross Thompson
aa04778d0b Cache fsm simplifications. 2022-02-11 15:16:45 -06:00
Ross Thompson
e6c8cfd49b Removed STATE_CPU_BUSY_FINISH_AMO from cache. This is redundant with STATE_CPU_BUSY. 2022-02-11 15:09:00 -06:00
Ross Thompson
83adacbee3 Simplified cache fsm. 2022-02-11 14:54:57 -06:00
Ross Thompson
c8e6884926 Fixed bug. 
It was possible for DTLBMissM to prevent a dcache flush.
 2022-02-11 14:00:01 -06:00
Ross Thompson
b1cba4be2b Updates to linux wave. 2022-02-11 13:28:18 -06:00
Ross Thompson
9145a96b53 Updated linux wave. 2022-02-11 13:15:42 -06:00
Ross Thompson
3f4ae91468 linux wave cleanup. 2022-02-11 10:48:45 -06:00
Ross Thompson
20456097cd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-11 10:47:21 -06:00
Ross Thompson
2f2a4f4500 Fixed subtle and infrequenct bug. 
Loading buildroot at 483M instructions started with a spill + ITLBMiss.  The spillsupport logic allowed transition to the second access only after the bus/cache completed the first operation.  However the BusStall was suppressed if ITLBMissF occurs resulting in the spillfsm advancing to the second operation.  Now the spill logic also takes in ITLBMissF and prevents the early transition to the second access.
 2022-02-11 10:46:06 -06:00
David Harris
15fb7fee60 Cleaned up synthesis warnings 2022-02-11 01:15:16 +00:00
David Harris
901a64e052 merged synth.tcl 2022-02-11 00:21:24 +00:00
David Harris
fdcb45d779 Waive some synthesis warning messages 2022-02-11 00:20:23 +00:00
Ross Thompson
fc6dc52618 Fixed bugs in ifu spills and missing reset on bus data register. 2022-02-10 18:11:57 -06:00
James Stine
8cc1375bbe Slight tweaks to synthDC for library variables 2022-02-10 17:56:27 -06:00
Ross Thompson
4e3a13ecc6 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-10 17:52:27 -06:00
Ross Thompson
9ad4523b9d Updated wave files to reflect recent changes. 2022-02-10 17:52:19 -06:00
James Stine
59b2997aa6 fix booboos from last push 2022-02-10 17:42:44 -06:00
James Stine
55394415db Slight tweak to the great additions to the synthesis scripts. Pulls lib from addin directory by default for sky130. Also changed name from 90 and 130 to sky90 and sky130, respectively. 2022-02-10 17:30:00 -06:00
Ross Thompson
f23817bf69 Replacement policy cleanup. 2022-02-10 11:42:40 -06:00
Ross Thompson
411997010b Replacement policy cleanup. 2022-02-10 11:40:10 -06:00
Ross Thompson
382d5fab0f Cleanup. 2022-02-10 11:27:15 -06:00
Ross Thompson
3a0af5d9e9 Cleanup + critical path optimizations. 2022-02-10 11:11:16 -06:00
Ross Thompson
fc68c2f09a Cache name clarifications. 2022-02-10 10:50:17 -06:00
Ross Thompson
e00d404154 More cache cleanup. 2022-02-10 10:43:37 -06:00
Ross Thompson
65803ebe98 structural muxes. 2022-02-09 19:36:21 -06:00
Ross Thompson
21364dae32 Ignore saif files. 2022-02-09 19:30:26 -06:00
Ross Thompson
2a989e6d05 More cache cleanup. 2022-02-09 19:29:15 -06:00
Ross Thompson
3b8ad3f7c7 Cleaned up comments. 2022-02-09 19:21:35 -06:00
Ross Thompson
911ee36b22 Removed all possilbe paths to PreSelAdr from TrapM. 2022-02-09 19:20:10 -06:00
Ross Thompson
459cd3c450 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-09 19:14:39 -06:00
Ross Thompson
c015bae64a Added explainations of synthesis variables in README. 2022-02-09 18:47:20 -06:00
Ross Thompson
976cd5a884 Added saif to synthDC flow. 2022-02-09 18:42:48 -06:00
Ross Thompson
327a05c9d8 Added commented out commands to generate saif file from vsim. 2022-02-09 18:40:45 -06:00
bbracker
05dd37d3d6 rename dump-dts debug script 2022-02-10 00:10:09 +00:00
bbracker
f823338597 continue to rename devicetree to wally-virt 2022-02-10 00:08:28 +00:00
bbracker
62d1ed65d4 rename devicetree to wally-virt 2022-02-10 00:07:29 +00:00
Ross Thompson
21f6feb510 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-09 16:44:33 -06:00
Ross Thompson
c7a2e6cb06 Commented quit. 2022-02-09 16:44:26 -06:00
James E. Stine
13e826561f Update on README.md for synthDC 2022-02-09 16:20:05 -06:00
Ross Thompson
d1e79aaea5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-02-09 16:11:31 -06:00
Ross Thompson
bb092a9dff Added support for 90nm. 2022-02-09 16:06:27 -06:00
James E. Stine
216e050ecf Add power analysis to synth.tcl 2022-02-09 16:04:20 -06:00
Ross Thompson
ed4e912413 Cleaned up synthesis flow. 2022-02-09 15:18:49 -06:00
Ross Thompson
04cf60a6bf Updated synthesis and Makefile to output into binned directories. 2022-02-09 15:06:42 -06:00
David Harris
12dfcd8213 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-02-09 19:47:52 +00:00
David Harris
cb86e1cda9 Merged synthesiss scripts into main 2022-02-09 19:47:50 +00:00
bbracker
440cac9f77 minor interrupt syntax fix 2022-02-09 02:56:39 +00:00
bbracker
789ce53355 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-02-09 02:30:00 +00:00
bbracker
84ffdfc8c4 add tracegen support for interrupt parsing 2022-02-09 02:29:47 +00:00