1672 Commits

Author	SHA1	Message	Date
David Harris	c306884e2c	Adding custom Wally test infrastructure	2021-11-01 08:48:46 -07:00
bbracker	38d26e857b	fix buildroot graphical sim	2021-10-31 18:33:43 -07:00
David Harris	e9244e7a85	Fixed exe2memfile parsing of weird line in arch64d test	2021-10-30 07:26:18 -07:00
David Harris	f35b31f166	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-10-29 22:32:08 -07:00
David Harris	717f9d48e9	tesgen cleanup, added riscv-arch-test D tests	2021-10-29 22:31:48 -07:00
David Harris	f7acd31bcb	rearranging testgen	2021-10-29 22:28:37 -07:00
Ross Thompson	8aad95366d	Fixed the 4 way set associative pseudo LRU replacement policy.	2021-10-29 12:46:02 -05:00
Ross Thompson	f61fcd25a9	Possible fix for the incorrect behavior of the pseudo LRU replacement policy for 4 ways set associative caches.	2021-10-29 11:03:37 -05:00
Ross Thompson	54c714d222	Applied batch from fpga branch which fixes the dcache fence bug. The should cause the dcache to flush all dirty cache lines to main memory. The bug caused the dirty reset to clear each way for a particular line.	2021-10-28 11:07:18 -05:00
bbracker	fe2bf13720	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-10-27 14:40:31 -07:00
bbracker	d14fa074ec	checkpoint generator off-by-one error fix	2021-10-27 14:10:29 -07:00
Noah Limpert	21ea270fe2	Have replaced .* with signal names in ifu	2021-10-27 13:45:37 -07:00
koooo142857	0a33b0904d	aligned all files in ifu folder	2021-10-27 12:43:55 -07:00
David Harris	e62b57e2c2	commented out some failing FPU tests	2021-10-27 11:27:34 -07:00
David Harris	9cfb8deaab	Fixed FResultSelM to select proper flags	2021-10-27 11:02:42 -07:00
David Harris	31a2346c37	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-10-27 10:37:46 -07:00
David Harris	0421b7af56	Changes for floating point sims	2021-10-27 10:37:35 -07:00
Ross Thompson	fed8882aec	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-10-27 09:59:55 -05:00
Ross Thompson	d98baf90a3	Replaced async reset flip flops with sync reset flip flops in cache and bpread.	2021-10-27 09:57:11 -05:00
bbracker	52529db40b	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-10-26 12:43:48 -07:00
bbracker	1409dc48a8	bugfix argument passing to GDB script; remove outdated GDB script	2021-10-26 12:43:42 -07:00
David Harris	f793dd7a5e	removed unused signal from wave.do	2021-10-26 09:02:22 -07:00
David Harris	7d516c65e7	commented out nonworking tests	2021-10-26 08:56:49 -07:00
David Harris	ca700610f8	removed referenc outputs	2021-10-26 08:51:49 -07:00
David Harris	1a6fb2fad9	Forgot to save cacheway merge	2021-10-26 08:38:13 -07:00
David Harris	79c1395967	merging changes	2021-10-26 08:34:36 -07:00
David Harris	44de52a05a	Synchronous reset in non-flop blocks	2021-10-26 08:30:35 -07:00
Ross Thompson	09b3549efd	Fixed another critical path in the caches.	2021-10-25 22:05:11 -05:00
Ross Thompson	cb7015a690	Fixed the timing issue in the cache replacement polcy.	2021-10-25 18:00:23 -05:00
Ross Thompson	6c92d3267f	Fixed bug with the changes to sram1rw.	2021-10-25 16:11:41 -05:00
Ross Thompson	c963ea1a64	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-10-25 15:36:21 -05:00
Ross Thompson	694b3fbb6f	Possible fix for critical path timing in caches.	2021-10-25 15:33:33 -05:00
bbracker	f39a509b5b	adapt testbench linux to use reset_ext	2021-10-25 13:26:44 -07:00
bbracker	f50787203f	copy / link to checkpoint 8500000 dir	2021-10-25 13:24:02 -07:00
bbracker	2c9c9328a9	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2021-10-25 12:25:37 -07:00
bbracker	c61cbf9618	change CHECKPOINT to be a parameter (not a macro) so that do scripts can control it; clean up checkpoint initialization macros	2021-10-25 12:25:32 -07:00
David Harris	14e6d2c576	Converted flops to synchronous reset now that reset signal is synchronized	2021-10-25 11:49:20 -07:00
David Harris	47124f36c8	Added synchronizer to reset	2021-10-25 10:05:41 -07:00
bbracker	b51e4d504b	some linux testbench cleanup	2021-10-25 10:04:30 -07:00
Ross Thompson	ebef47b1c9	Modified the cache's sram model so if it used to synthesize flip flops it terminates the read critical path at the address's input rather than the output read data.	2021-10-24 21:21:49 -05:00
bbracker	d348ebffda	checkpoint initialization bugfix	2021-10-24 18:39:51 -07:00
bbracker	9423b90780	switch linux graphical sim over to Ross's waves	2021-10-24 18:39:23 -07:00
bbracker	9cdbd9a0bf	remove unused scripts	2021-10-24 15:19:03 -07:00
bbracker	4100ed9a7a	update debugger script to new style	2021-10-24 15:18:44 -07:00
bbracker	3c118437de	fix typo	2021-10-24 15:05:00 -07:00
bbracker	eb9740bc31	manually resolved git merge conflicts in testbench linux after checkpointing	2021-10-24 15:02:19 -07:00
bbracker	0a32d79370	checkpoint generator bugfix	2021-10-24 14:46:56 -07:00
Ross Thompson	87aaec3b6c	Partial cleanup of unused signals in caches and bpred.	2021-10-24 15:04:20 -05:00
bbracker	4544d28bc9	or actually needed to reduce expectations of buildroot	2021-10-24 06:59:34 -07:00
bbracker	23bff55c6e	increase regression's expectations of buildroot	2021-10-24 06:50:22 -07:00