Ross Thompson
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6bd447d570
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Patched the ILA's debug2.xdc constraint file to work with the wally memory design.
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2022-01-06 15:18:18 -06:00 |
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David Harris
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2b4c81fe98
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Fixed unpacking bug; regression runs again
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2022-01-06 18:22:30 +00:00 |
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David Harris
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55e757db03
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-01-06 18:10:32 +00:00 |
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David Harris
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c9aa21d5a3
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FPU debug and configurable logic cleanup
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2022-01-06 18:10:25 +00:00 |
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Ross Thompson
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8c71daff11
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-01-06 11:56:23 -06:00 |
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Ross Thompson
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42623141cd
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Updated fpga ILA constraints to match the new changes to the rtl.
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2022-01-06 11:56:09 -06:00 |
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Ross Thompson
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7f66177769
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Fixed bug in synthesis script.
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2022-01-05 23:07:36 -06:00 |
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Ross Thompson
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d30ad136f3
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cleaned up cacheway and sram1rw.sv. also noticed possible bug in sram1rw.sv.
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2022-01-05 22:56:18 -06:00 |
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Ross Thompson
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365b2715ed
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More name cleanup in cache.
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2022-01-05 22:37:53 -06:00 |
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Ross Thompson
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77efcad15b
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Changed names of address in caches.
Removed old cache files.
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2022-01-05 22:19:36 -06:00 |
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Ross Thompson
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5a2ae561a7
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Updates to support fpga.
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2022-01-05 18:07:23 -06:00 |
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Ross Thompson
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3517db6b64
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Fixed xilinx synth error with $error in extend.sv
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2022-01-05 17:48:08 -06:00 |
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Kip Macsai-Goren
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1556fb967d
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fixed 32 vs 64 bit copying error
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2022-01-05 23:14:12 +00:00 |
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Ross Thompson
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fb3207fc72
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-01-05 16:57:29 -06:00 |
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Ross Thompson
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8d33bf0b4a
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Slower but correct implementation of flush.
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2022-01-05 16:57:22 -06:00 |
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David Harris
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e33db012ba
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Reinstated many arch f/d tests that had failed because of memfile issues
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2022-01-05 22:44:10 +00:00 |
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David Harris
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31067c8e7d
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Restored many of the arch32f and arch64d that had been failing because of memfile issues
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2022-01-05 22:23:46 +00:00 |
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David Harris
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643732b552
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-01-05 22:10:50 +00:00 |
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Kip Macsai-Goren
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e8780878b6
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-01-05 22:10:37 +00:00 |
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David Harris
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30c1ab5213
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-01-05 22:10:33 +00:00 |
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David Harris
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355efda9bc
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Replaced exe2memfile with SiFive elf2hex
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2022-01-05 22:10:26 +00:00 |
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Kip Macsai-Goren
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172b6190f4
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updated pma tests for simpler test lib
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2022-01-05 22:10:12 +00:00 |
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kipmacsaigoren
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980bc8067a
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Added the config file to the outputs of synth
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2022-01-05 16:08:31 -06:00 |
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Kip Macsai-Goren
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bf062e2ed7
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updated tests to make correctly with output verification
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2022-01-05 21:43:15 +00:00 |
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Kip Macsai-Goren
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4efe6813dd
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allowed option for tests to make without spike simulation. added postverify back in for outputs
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2022-01-05 21:17:54 +00:00 |
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Kip Macsai-Goren
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1a9de1fae5
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updated pma tests to match simpler test library. They don't pass regression yet
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2022-01-05 21:13:40 +00:00 |
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Kip Macsai-Goren
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fb8984c8cf
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-01-05 20:17:52 +00:00 |
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Ross Thompson
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75788dd9c2
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Changes to wave file.
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2022-01-05 14:16:59 -06:00 |
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Ross Thompson
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bd901cd125
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-01-05 14:15:27 -06:00 |
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Ross Thompson
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49eea2add5
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Fixed bug with flush dirty not cleared in the correct cache line.
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2022-01-05 14:14:01 -06:00 |
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davidharrishmc
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20b13a4895
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Update README.md
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2022-01-05 11:29:54 -08:00 |
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Kip Macsai-Goren
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7abddf8719
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-01-05 18:38:29 +00:00 |
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James E. Stine
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64b4981ca1
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-01-05 10:44:28 -06:00 |
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James E. Stine
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17e9ff4610
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Add script to generate memfile using elf2hex
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2022-01-05 10:44:01 -06:00 |
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David Harris
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85fa620cfb
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Finished removing generate statements
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2022-01-05 16:41:17 +00:00 |
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David Harris
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32590d484c
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Removed more generate statements
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2022-01-05 16:25:08 +00:00 |
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David Harris
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f04856ee94
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Removed more generate statements
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2022-01-05 16:01:03 +00:00 |
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David Harris
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c1d6550ccb
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Removed generate statements
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2022-01-05 14:35:25 +00:00 |
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Ross Thompson
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f89c1d91dc
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Renamed most signals inside cache.sv so they are agnostic to i or d.
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2022-01-04 23:52:42 -06:00 |
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Ross Thompson
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9eda7c12bd
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the i and d caches now share common verilog.
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2022-01-04 23:40:37 -06:00 |
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Ross Thompson
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b06c3b8acd
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parameterized the caches with the goal of using common rtl for both i and d caches.
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2022-01-04 22:40:51 -06:00 |
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Ross Thompson
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06168e67e4
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Switched block for line in caches.
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2022-01-04 22:08:18 -06:00 |
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Ross Thompson
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d94a1c6404
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Fixed bug where last line of dcache was not written back to memory on dcache flush.
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2022-01-04 21:55:48 -06:00 |
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Ross Thompson
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0dd61a57da
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-01-04 18:41:52 -06:00 |
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Ross Thompson
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3c3c6d0fe8
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Fixed dcache flush.
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2022-01-04 18:40:58 -06:00 |
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David Harris
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08e6a10480
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Removed imperas mmu tests; using wallypriv instead
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2022-01-04 23:14:53 +00:00 |
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Kip Macsai-Goren
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17b9143d10
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cleaned up Imperas tests to pass make
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2022-01-04 21:32:21 +00:00 |
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Kip Macsai-Goren
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87ba45ce36
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-01-04 21:30:51 +00:00 |
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Kip Macsai-Goren
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0ee4e03cd6
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fixed arch tests to pass make, added 32 bit tests, addded all make-passing tests to tests.vh.
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2022-01-04 21:30:38 +00:00 |
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David Harris
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57daff45c8
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Fixed bad address for F/fmsub_b18-01
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2022-01-04 21:04:06 +00:00 |
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