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updated pma tests to match simpler test library. They don't pass regression yet
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Kip Macsai-Goren
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//
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// WALLY-PMA
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//
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// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu> (Copied heavily from SV48 test).
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// Author: Kip Macsai-Goren <kmacsaigoren@g.hmc.edu>
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//
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// Created 2021-06-15
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//
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@ -40,25 +40,109 @@
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# ---------------------------------------------------------------------------------------------
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# =========== test 12.3.2.1 PMAs: Memory Access Size, Type protection test ===========
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# Tests memory load, store, and /* *** execute? */ permissions based on table 12.3 in the *** riscv book, copied below
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# Tests memory load, store, and execute permissions based on table 12.3 in the *** riscv book, copied below
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# Test 12.3.2.1.1 check enabled devices
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# | Region | Read widths | R | W | X | Cacheable | Idempotent | Atomic |
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.8byte 0x1000, 0x0, 0xB # | ROM | Any | YES | NO | YES | YES | NO | NO | # *** Impossible to write? how am I supposed to put a known value in ROM to read out?
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.8byte 0x2000000, 0x0, 0xB # | CLINT | Any | YES | YES | NO | NO | NO | NO |
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.8byte 0xC000000, 0x0, 0xB # | PLIC | 32-bit | YES | YES | NO | NO | NO | NO |
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.8byte 0x10000000, 0x0, 0xB # | UART0 | 8-bit | YES | YES | NO | NO | NO | NO |
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.8byte 0x20000000, 0x0, 0xB # | GPIO | 32-bit | YES | YES | NO | NO | NO | NO |
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.8byte 0x800F0000, 0x0, 0xB # | DRAM | Any | YES | YES | YES | YES | YES | YES |
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# *** the dram one has a little offset so we don't accidentally write over the code of this test.
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# | Region | Base Address | Read widths | R | W | X | Cacheable | Idempotent | Atomic |
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# | ROM | 0x1000 | Any | YES | NO | YES | YES | NO | NO |
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# | CLINT | 0x2000000 | Any | YES | YES | NO | NO | NO | NO |
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# | PLIC | 0xC000000 | 32-bit | YES | YES | NO | NO | NO | NO |
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# | UART0 | 0x10000000 | 8-bit | YES | YES | NO | NO | NO | NO |
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# | GPIO | 0x1012000 | 32-bit | YES | YES | NO | NO | NO | NO |
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# | DRAM | 0x80000000 | Any | YES | YES | YES | YES | YES | YES |
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# Test 12.3.2.1.2 Check Regions with no enabled device fail all
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.8byte 0x0000, 0x0, 0xC
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.8byte 0x3000, 0x0, 0xC
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.8byte 0x4000000, 0x0, 0xC
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.8byte 0xE0000000, 0x0, 0xC
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.8byte 0x12000000, 0x0, 0xC
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.8byte 0xA0000000, 0x0, 0xC
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# ************** Cacheable, Idempotent, Atomic tests are not implemented yet.
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# ----------------- ROM ---------------------
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# *** the rom is read only and these read tests depend on reading a known value out of memory.
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# Is there some guaranteed value that I can read out of the ROM
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# otherwise the read test can be modified to just check that the read happened,
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# not necessarily that it got a known value out of memory. This feels hacky and Id be interested in other options.
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# .8byte 0x1000, 0x0000DEADBEEF0000, 0x0 # 64-bit write: store access fault
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# .8byte 0x1000, 0x0000DEADBEEF0000, 0x1 # 64-bit read: success
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# .8byte 0x1000, 0x0000DEADBEEF0001, 0x11 # 32-bit write: store access fault
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# .8byte 0x1000, 0x0000DEADBEEF0001, 0x14 # 32-bit read: success
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# .8byte 0x1000, 0x0000DEADBEEF0002, 0x12 # 16-bit write: store access fault
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# .8byte 0x1000, 0x0000DEADBEEF0002, 0x15 # 16-bit read: success
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# .8byte 0x1000, 0x0000DEADBEEF0003, 0x13 # 08-bit write: store access fault
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# .8byte 0x1000, 0x0000DEADBEEF0003, 0x16 # 08-bit read: success
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# # *** similar problem with the execute tests. Impossible to write the needed executable code into rom once the program's running
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# .8byte 0x1000, 0x111, 0x2 # execute: success
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# ----------------- CLINT ---------------------
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.8byte 0x2000000, 0x0000DEADBEEF00B4, 0x0 # 64-bit write: success
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.8byte 0x2000000, 0x0000DEADBEEF00B4, 0x1 # 64-bit read: success
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.8byte 0x2000000, 0x0000DEADBEEF00B5, 0x11 # 32-bit write: success
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.8byte 0x2000000, 0x0000DEADBEEF00B5, 0x14 # 32-bit read: success
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.8byte 0x2000000, 0x0000DEADBEEF00B6, 0x12 # 16-bit write: success
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.8byte 0x2000000, 0x0000DEADBEEF00B6, 0x15 # 16-bit read: success
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.8byte 0x2000000, 0x0000DEADBEEF00B7, 0x13 # 08-bit write: success
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.8byte 0x2000000, 0x0000DEADBEEF00B7, 0x16 # 08-bit read: success
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.8byte 0x2000000, 0xbad, 0x2 # execute: instruction access fault
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# ----------------- PLIC ---------------------
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.8byte 0xC000000, 0x0000DEADBEEF00B8, 0x0 # 64-bit write: store access fault
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.8byte 0xC000000, 0x0000DEADBEEF00B8, 0x1 # 64-bit read: load access fault
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.8byte 0xC000000, 0x0000DEADBEEF00B9, 0x11 # 32-bit write: success
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.8byte 0xC000000, 0x0000DEADBEEF00B9, 0x14 # 32-bit read: success
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.8byte 0xC000000, 0x0000DEADBEEF00BA, 0x12 # 16-bit write: store access fault
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.8byte 0xC000000, 0x0000DEADBEEF00BA, 0x15 # 16-bit read: load access fault
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.8byte 0xC000000, 0x0000DEADBEEF00BB, 0x13 # 08-bit write: store access fault
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.8byte 0xC000000, 0x0000DEADBEEF00BB, 0x16 # 08-bit read: load access fault
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.8byte 0xC000000, 0xbad, 0x2 # execute: instruction access fault
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# ----------------- UART0 ---------------------
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.8byte 0x10000000, 0x0000DEADBEEF00BC, 0x0 # 64-bit write: store access fault
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.8byte 0x10000000, 0x0000DEADBEEF00BC, 0x1 # 64-bit read: load access fault
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.8byte 0x10000000, 0x0000DEADBEEF00BD, 0x11 # 32-bit write: store access fault
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.8byte 0x10000000, 0x0000DEADBEEF00BD, 0x14 # 32-bit read: load access fault
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.8byte 0x10000000, 0x0000DEADBEEF00BE, 0x12 # 16-bit write: store access fault
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.8byte 0x10000000, 0x0000DEADBEEF00BE, 0x15 # 16-bit read: load access fault
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.8byte 0x10000000, 0x0000DEADBEEF00BF, 0x13 # 08-bit write: success
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.8byte 0x10000000, 0x0000DEADBEEF00BF, 0x16 # 08-bit read: success
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.8byte 0x10000000, 0xbad, 0x2 # execute: instruction access fault
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# ----------------- GPIO ---------------------
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.8byte 0x1012000, 0x0000DEADBEEF00C0, 0x0 # 64-bit write: store access fault
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.8byte 0x1012000, 0x0000DEADBEEF00C0, 0x1 # 64-bit read: load access fault
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.8byte 0x1012000, 0x0000DEADBEEF00C1, 0x11 # 32-bit write: success
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.8byte 0x1012000, 0x0000DEADBEEF00C1, 0x14 # 32-bit read: success
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.8byte 0x1012000, 0x0000DEADBEEF00C2, 0x12 # 16-bit write: store access fault
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.8byte 0x1012000, 0x0000DEADBEEF00C2, 0x15 # 16-bit read: load access fault
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.8byte 0x1012000, 0x0000DEADBEEF00C3, 0x13 # 08-bit write: store access fault
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.8byte 0x1012000, 0x0000DEADBEEF00C3, 0x16 # 08-bit read: load access fault
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.8byte 0x1012000, 0xbad, 0x2 # execute: instruction access fault
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# ----------------- DRAM ---------------------
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# the following is already tested by the fact that this test runs without error:
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# 64 bit reads and writes into DRAM,
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# Execution in DRAM
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# offset by 0xf000 to avoid overwriting the program
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.8byte 0x8000F000, 0x0000DEADBEEF00C4, 0x11 # 32-bit write: success
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.8byte 0x8000F000, 0x0000DEADBEEF00C4, 0x14 # 32-bit read: success
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.8byte 0x8000F000, 0x0000DEADBEEF00C5, 0x12 # 16-bit write: success
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.8byte 0x8000F000, 0x0000DEADBEEF00C5, 0x15 # 16-bit read: success
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.8byte 0x8000F000, 0x0000DEADBEEF00C6, 0x13 # 08-bit write: success
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.8byte 0x8000F000, 0x0000DEADBEEF00C6, 0x16 # 08-bit read: success
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# ----------------- Inaccessible ---------------------
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# show that load, store, and jalr cause faults in a region not defined by PMAs.
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# *** should I go through every possible inaccessible region of memory or is one just fine?
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.8byte 0xD000000, 0x0000DEADBEEF00C7, 0x0 # 64-bit write: store access fault
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.8byte 0xD000000, 0x0000DEADBEEF00C7, 0x1 # 64-bit read: load access fault
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.8byte 0x1000, 0x111, 0x2 # execute: instruction access fault
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.8byte 0x0, 0x0, 0x3 // terminate tests
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