slmnemo
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be658d3933
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Reworked AHB fsm to support one cycle latency read and writes, renamed key signals to better reflect their use, and fixed HTRANS errors
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2022-06-08 15:03:15 -07:00 |
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slmnemo
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a5aa75e5de
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Merge branch 'main' into cacheburstmode
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2022-06-08 02:21:33 +00:00 |
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slmnemo
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1d22fc707a
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Added lock signal to ensure AHB speaks with the right bus
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2022-06-08 02:19:21 +00:00 |
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slmnemo
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90c5e5d319
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Reworked bus to handle burst interfacing
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2022-06-07 11:22:53 +00:00 |
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David Harris
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9065b684f8
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Added stalls for pending SFENCE.VMA and FENCE.I in hazard unit
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2022-06-02 09:37:59 -07:00 |
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David Harris
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129fab3794
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Provided sfencevmaM to hazard unit and renamed TLBFlush signals to sfencevma going into LSU/IFU. Preparing for SFENCE.VMA to flush the pipeline, but that is not yet working.
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2022-06-02 14:18:55 +00:00 |
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slmnemo
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efce3e4953
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added LSUBurstDone signal to signal when a burst has finished
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2022-05-26 16:29:13 -07:00 |
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slmnemo
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80965f953c
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added burst size signals to the IFU, EBU, LSU, and busdp
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2022-05-25 18:02:50 -07:00 |
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David Harris
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4c5e361b00
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More unused signal cleanup
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2022-05-12 15:26:08 +00:00 |
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David Harris
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5acb526375
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More unused signal cleanup
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2022-05-12 15:21:09 +00:00 |
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David Harris
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fb725a9e0a
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Clean up unused signals
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2022-05-12 14:49:58 +00:00 |
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David Harris
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a8c9f504fa
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Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt
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2022-05-11 15:08:33 +00:00 |
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David Harris
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91472eb948
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Removed M suffix from interrupts because they are generated asynchronously to pipeline
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2022-05-11 14:41:55 +00:00 |
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David Harris
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8066ba45e8
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Preliminary support for big endian modes. Regression passes but no big endian tests written yet.
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2022-05-08 06:46:35 +00:00 |
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David Harris
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2cdd49c7d2
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WFI terminates when an interrupt is pending even if interrupts are globally disabled
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2022-05-08 04:30:46 +00:00 |
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David Harris
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7024293a59
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Zero'd wfiM when ZICSR not supported to fix hang in E tests
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2022-05-05 15:32:13 +00:00 |
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David Harris
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94459ade3d
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Changed WFI to stall pipeline in memory stage
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2022-05-05 02:03:44 +00:00 |
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David Harris
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9c4de0e9c1
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FPU generates illegal instruction if MSTATUS.FS = 00
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2022-05-03 11:56:31 +00:00 |
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Kip Macsai-Goren
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7bc6943527
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Changed mtval for instruction misaligned fault to get address from ieuAdrM (Jal/branch target address)
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2022-04-22 22:46:11 +00:00 |
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Ross Thompson
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5ef6cde52e
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Added more ILA signals.
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2022-04-02 16:39:45 -05:00 |
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bbracker
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54b9745a75
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big interrupts refactor
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2022-03-30 13:22:41 -07:00 |
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bbracker
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46ffa4b079
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fix typo that Madeleine found
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2022-03-28 15:39:29 -07:00 |
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bbracker
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150a7b234b
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tabs vs spaces disagreement
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2022-03-24 17:11:41 -07:00 |
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bbracker
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9f60256f22
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1st attempt at multiple channel PLIC
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2022-03-24 17:08:10 -07:00 |
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Ross Thompson
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58668812c1
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Moved WriteDataM register into LSU.
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2022-03-23 14:17:59 -05:00 |
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Ross Thompson
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62f5f1e622
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Broken state. address translation not working after changes to hptw to support atomic updates to PT.
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2022-02-16 23:37:36 -06:00 |
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Ross Thompson
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1bb8d36308
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Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.
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2022-01-27 17:11:27 -06:00 |
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David Harris
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ca1f7ce5d3
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Renamed wallypipelinedhart to wallypipelinedcore
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2022-01-20 16:02:08 +00:00 |
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