411 Commits

Author	SHA1	Message	Date
Ross Thompson	bdfca503fa	Name cleanup.	2022-03-10 18:44:50 -06:00
Ross Thompson	d77adbd673	Signal name cleanup.	2022-03-10 18:26:58 -06:00
Ross Thompson	5c16b65a16	simplified uncore's name for HWDATA.	2022-03-10 18:17:44 -06:00
Ross Thompson	543e10ab32	Moved subwordwrite to lsu directory.	2022-03-10 18:15:25 -06:00
Ross Thompson	54abd944e2	Simplified byte write enable logic.	2022-03-10 18:13:35 -06:00
Ross Thompson	50789f9ddd	Byte write enables are passing all configs now.	2022-03-10 17:26:32 -06:00
Ross Thompson	f7df3a0666	Progress on the path to getting all configs working with byte write enables.	2022-03-10 17:02:52 -06:00
Ross Thompson	83133f8c47	Partially working byte write enables. Works for cache, but not dtim or bus only.	2022-03-10 16:11:39 -06:00
Ross Thompson	d5f524a15e	Added byte write enables to cache SRAMs.	2022-03-10 15:48:31 -06:00
David Harris	b1340653cf	bit write update	2022-03-09 19:09:20 +00:00
David Harris	004853c312	Refactored SRAM bit write enable	2022-03-09 17:49:28 +00:00
David Harris	ba9320d822	Updated testbench to read expected flags	2022-03-09 13:58:17 +00:00
Ross Thompson	2a8a1cd191	Minor cleanup to interlockfsm.	2022-03-08 23:38:58 -06:00
Ross Thompson	ac9528b450	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-03-08 18:05:35 -06:00
Ross Thompson	ed32801cc1	Comments.	2022-03-08 18:05:25 -06:00
Ross Thompson	534fd70f76	Marked signals for name changes.	2022-03-08 17:41:02 -06:00
David Harris	5d0b9bab6e	Added more test cases and rounding modes to fma test generator	2022-03-08 23:29:29 +00:00
David Harris	582b943380	fixed setup.sh merge conflict	2022-03-08 23:21:06 +00:00
David Harris	cfa82efccc	fma16_testgen.c test cases	2022-03-08 23:18:18 +00:00
Ross Thompson	acd60218b8	Removed unused signal.	2022-03-08 16:58:26 -06:00
Ross Thompson	cc21414051	Added parameter to spillsupport.	2022-03-08 16:38:48 -06:00
Ross Thompson	60e6c1ffa7	Moved cacheable signal into cache.	2022-03-08 16:34:02 -06:00
bbracker	51e68819c4	fix up PLIC and UART checkpointing	2022-03-07 23:48:47 -08:00
bbracker	c2ac18b5de	change testbench-linux.sv to use new shared location of disassembly files	2022-03-07 20:04:08 -08:00
David Harris	d2282d5e87	Checked in fma16_template.v	2022-03-06 13:29:35 +00:00
David Harris	9fd861a9ee	removed more old 64priv tests	2022-03-04 03:57:19 +00:00
bbracker	51f1a411dd	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-03-04 00:12:00 +00:00
bbracker	1c5697874f	comment out nonfunctioning CSR-PERMISSIONS-M test	2022-03-04 00:11:55 +00:00
David Harris	63e9d846e4	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-03-04 00:07:34 +00:00
David Harris	48705457d5	LSU/Cache code review notes	2022-03-04 00:07:31 +00:00
bbracker	efb5d1dbc0	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-03-04 00:06:27 +00:00
bbracker	443dd40ea8	remove imperas32p tests	2022-03-04 00:06:18 +00:00
David Harris	545f569f78	Fixed fma files to stop breaking synthesis. Changed Makefiles to skip Imperas	2022-03-03 15:38:08 +00:00
David Harris	080fef6436	erge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-03-02 23:47:16 +00:00
David Harris	8fbdbba81a	fma file fixes	2022-03-02 23:47:01 +00:00
bbracker	e28ca531e0	fix peripheral test and add it to regression	2022-03-02 23:44:39 +00:00
bbracker	be2f668867	but apparently QEMU doesn't show UXL in SSTATUS	2022-03-02 22:44:19 +00:00
bbracker	01e0f2f0d2	update SXL UXL bits in MSTATUS to match new QEMU trace	2022-03-02 22:15:57 +00:00
bbracker	c1290d493f	add CSRs to waveview	2022-03-02 18:31:10 +00:00
bbracker	d7b8c9d877	add rv32a tests to regression	2022-03-02 17:54:55 +00:00
bbracker	6c422cd357	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-03-02 17:46:40 +00:00
David Harris	3bea7bb431	removed imperas-riscv-tests	2022-03-02 17:28:20 +00:00
bbracker	5f5cc514b8	fix buildroot checkpointing and add it back to regression	2022-03-02 16:00:19 +00:00
bbracker	4f22a55dd4	add LRSC test and add wally64a to regression	2022-03-02 07:09:37 +00:00
David Harris	1661983345	FMA project ready to start	2022-03-01 20:58:08 +00:00
bbracker	41b3912abc	buildroot graphical sim bugfix	2022-03-01 03:24:23 +00:00
bbracker	04ace8c154	switch linux-testbench infrastructure over to new linux testvectors at /opt/riscv	2022-03-01 03:11:43 +00:00
bbracker	d620fb4442	deprecate imperas64p tests and move them over to the privilege configuration of wally-riscv-arch-test	2022-03-01 00:37:46 +00:00
David Harris	f314e60dc8	Renamed unpacking unit to unpack and renamed WriteDataW to ResultW in IEU datapath	2022-02-28 20:50:51 +00:00
David Harris	f0a7ae2bba	adrdecs comments	2022-02-28 20:33:41 +00:00