6 Commits

Author	SHA1	Message	Date
David Harris	bdf1a8ba73	changed DMEM and IMEM configurations to support BUS/TIM/CACHE	2022-02-03 00:41:09 +00:00
David Harris	172a02551b	Removed Busybear and Buildroot Configuration	2022-02-02 20:32:22 +00:00
David Harris	c6adb7b6b1	Updated configs to fix GPIO address to match FU540	2022-01-26 18:16:34 +00:00
Ross Thompson	5726b5b640	Added support for logic memory in the IFU and LSU. This disables the bus interface. Peripherals do not work. Also requires using testbench-harvard.sv. I hope to merge this testbench with the main testbench.sv soon.	2022-01-13 22:21:43 -06:00
Ross Thompson	888a60d8d6	Switched block for line in caches.	2022-01-04 22:08:18 -06:00
David Harris	115287adc8	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00