Github_Repos/cvw
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4,755 Commits 5 Branches 2 Tags 53 MiB
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24 Commits

Author SHA1 Message Date
Ross Thompson
5d844801d2 Fixed problems with changes to ram2p. 2022-12-29 17:13:48 -06:00
Ross Thompson
5d91434b32 signal name changes in ram2p. 2022-12-27 15:07:01 -06:00
David Harris
8f0ef29349 Memory cleanup 2022-12-20 11:22:26 -08:00
David Harris
c26c3b76ea Renamed renamed sram to ram 2022-12-20 08:36:45 -08:00
David Harris
1ec62606f9 sram1p1rw cleanup 2022-12-20 02:57:51 -08:00
David Harris
0883736c88 Remoed unused bram modules 2022-12-20 02:40:45 -08:00
David Harris
9ad5552e89 Renamed SRAM2P1R1W to lower case 2022-12-20 02:09:55 -08:00
David Harris
b575f6242e Renamed SRAM2P1R1W to lower case 2022-12-20 02:09:36 -08:00
Ross Thompson
de538d1c2f Intermediate commit. Replaced flip flop dirty bit array with sram. 2022-11-30 00:08:31 -06:00
Ross Thompson
13e6f7d80b Changed names of cache signals. 2022-11-13 21:36:12 -06:00
David Harris
713df785d1 changed always_ff to always in sram1p1rw to fix testbench complaint 2022-09-25 19:56:40 -07:00
Ross Thompson
2eaf3af6c7 Removed the write first sram model. 2022-09-22 16:12:08 -05:00
Ross Thompson
b48d6b5e1f Solved the sram write first / read first issue. Works correctly with read first now. 2022-09-22 14:16:26 -05:00
Ross Thompson
3fb0a13fe2 Moved other SRAMs to generic/mem. 2022-09-21 12:36:03 -05:00
Ross Thompson
66c45949b5 Renamed brom1p1r to rom1p1r. 
removed used file bram2p1r1w.sv.
 2022-09-21 12:31:20 -05:00
Ross Thompson
ac864a6ca3 Merged together bram1p1rw with sram1p1rw as sram1p1rw. 
Fixed a major issue with the real SRAM implemenation.
 2022-09-21 12:20:00 -05:00
Ross Thompson
426ec6222b Added chip enables to sram. 2022-09-20 10:49:14 -05:00
Ross Thompson
5d2b299182 Fixed brom1p1r.sv to have fpga preload. 2022-09-02 15:49:50 -05:00
Ross Thompson
4d60d9a840 Fixed up FPGA constraints. 
Added back in the fpga boot rom preload.
 2022-09-02 13:54:35 -05:00
David Harris
19fe6d106c Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-25 09:52:49 -07:00
Ross Thompson
ad485fe591 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-08-25 09:03:34 -05:00
David Harris
3500286803 Cleanup typos 2022-08-25 04:32:19 -07:00
David Harris
f7209627c2 removed simpleram and modified dtim to use bram1p1rw 2022-08-25 03:39:57 -07:00
David Harris
a131e1f17a Added ROM module and moved memories into generic/mem 2022-08-24 17:03:22 -07:00