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867 Commits

Author SHA1 Message Date
David Harris
ae29eaa98d Simplified interface to fclassify and fsgn 2021-07-22 12:30:46 -04:00
Ross Thompson
42fe5ceee3 Cleaned up icache and dcache. 2021-07-22 11:06:44 -05:00
Ross Thompson
89e22bc5e8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-22 10:38:24 -05:00
Ross Thompson
e907d57340 Tested all numbers of ways for dcache 1, 2, 4, and 8. 2021-07-22 10:38:07 -05:00
bbracker
9dcd5d3622 fix UART RX FIFO bug where tail pointer can overtake head pointer 2021-07-22 02:09:41 -04:00
Ross Thompson
1e88784bd4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-21 16:44:32 -05:00
Kip Macsai-Goren
bb8ec549a7 fixed issue with tlbflush remaining high during a stalled sfence instruction 2021-07-21 17:43:36 -04:00
Ross Thompson
aa624625bc Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-21 16:39:07 -05:00
Ross Thompson
1f0ff804cf Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-21 14:56:30 -05:00
Ross Thompson
511c36fb1b Improved address bus names and usages in the walker, dcache, and tlbs. 
Merge branch 'walkerEnhance' into main
 2021-07-21 14:55:09 -05:00
Ross Thompson
abe57e3fd0 Added comment about better muxing. 2021-07-21 14:40:14 -05:00
Ross Thompson
3d79dc51bb 4 way set associative is now working. 2021-07-21 14:01:14 -05:00
Kip Macsai-Goren
e59490d032 Fixed TLB parameterization and valid bit flop to correctly do instr page faults 2021-07-21 14:44:43 -04:00
Katherine Parry
59f79722ab FDIV and FSQRT work 2021-07-21 14:08:14 -04:00
Ross Thompson
39fc9278ba Fixed remaining bugs in 2 way set associative dcache. 2021-07-21 10:35:23 -05:00
Ross Thompson
ba3aed8760 Finally fixed bug with the set associative design. The issue was not in the LRU but instead in the way selection mux. 
Also forgot to include cacheLRU.sv file.
 2021-07-20 23:17:42 -05:00
Katherine Parry
61f81bb76e FMA parameterized 2021-07-20 22:04:21 -04:00
Ross Thompson
8d0a552b5b Partially working 2 way set associative d cache. 2021-07-20 17:51:42 -05:00
bbracker
d6c93a50aa fix PC checking during InstrPageFault; fix order of S-mode CSR checking; rename peripheral scopes to not be genblk 2021-07-20 17:55:44 -04:00
David Harris
62b3673027 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-20 14:46:58 -04:00
David Harris
20744883df flag for optional boottim 2021-07-20 14:46:37 -04:00
Ross Thompson
bb5b5e71b1 Replaced FinalReadDataM with ReadDataM in dcache. 2021-07-20 13:27:29 -05:00
David Harris
c117356432 Parameterized I$/D$ configurations and added sanity check assertions in testbench 2021-07-20 08:57:13 -04:00
James E. Stine
b36d6fe1be slight mod to fpdiv - still bug in batch vs. non-batch 2021-07-20 01:47:46 -04:00
Ross Thompson
ae2371f2ce Added performance counters for dcache access and dcache miss. 2021-07-19 22:12:20 -05:00
David Harris
678f705415 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-19 18:19:59 -04:00
Kip Macsai-Goren
3a73ae0a8b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-19 16:46:46 -04:00
bbracker
78e513160e put MTIMECMP's reset value back to 0 because the reset value of -1 broke the MCAUSE tests 2021-07-19 16:19:24 -04:00
bbracker
76be84fa92 whoops MTIMECMP is always 64 bits 2021-07-19 15:40:53 -04:00
bbracker
fb6e618b1c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-19 15:13:14 -04:00
bbracker
77b690faf0 make testbench check the same CSRs that QEMU logs; change CLINT to reset MTIMECMP to -1 so that we don't instantly get a timer interrupt upon reset 2021-07-19 15:13:03 -04:00
Kip Macsai-Goren
c1c564d54c added changes to priority encoders from synthesis branch (correctly this time I hope) 2021-07-19 15:06:14 -04:00
Ross Thompson
5edd513f8c Furture simplification of the dcache ReadDataW update. 2021-07-19 12:46:31 -05:00
Ross Thompson
2ee97efb9c Fixed a complex bug in the dcache, where back to back loads would lose data on the load before a stall occurred. The solution was to modify the logic for SelAdrM in the dcache so that a stall would cause the SRAM to reread the address in the Memory stage rather than Execution stage. This also required updating the ReadDataWEn control so it is always enabled on ~StallW. 2021-07-19 12:32:16 -05:00
Ross Thompson
6ccbdc372d Broken. 
Possible change to walker, dcache, tlb addressing.
Improves the naming of address signals.
But has a problem when the walker finishes the dcache does not get the correct
address on the cycle the DTLB is updated.  This leads to incorrect index
selection in the dcache.
 2021-07-19 10:33:27 -05:00
bbracker
986b7a8252 change sram1rw to have a small delay so that we don't have signals changing on clock edges 2021-07-19 11:30:07 -04:00
David Harris
1b55f584c7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-19 10:34:18 -04:00
James Stine
62b4ef6953 delete sbtm_a4 and sbtm_a5 as they are not needed 2021-07-19 08:06:00 -05:00
James Stine
892bc68918 remove sbtm3.sv - not needed 2021-07-19 08:00:53 -05:00
James Stine
55f2720f89 update part I on sbtm change 2021-07-19 07:59:27 -05:00
David Harris
0c41b8102d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-19 00:25:06 -04:00
Katherine Parry
8d101548f1 FDIV and FSQRT passes when simulating in modelsim 2021-07-18 23:00:04 -04:00
David Harris
4729a72167 Updated FMA1 with parameterized size 2021-07-18 20:40:49 -04:00
David Harris
398e9583e9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-18 17:36:29 -04:00
David Harris
f22b6e7397 Added FLEN, NE, NF to config and started using these in FMA1 2021-07-18 17:28:25 -04:00
Katherine Parry
3527620c0b fdivsqrt inegrated, but not completley working 2021-07-18 14:03:37 -04:00
David Harris
e31d2ef9f5 Renamed pagetablewalker to hptw 2021-07-18 04:11:33 -04:00
David Harris
e962324d00 LSUArb: Removed Demuxes on ReadDataW, DataMiisalignedM, HPTWStall 2021-07-18 03:51:30 -04:00
David Harris
40c5d3ced7 HPTW: Simpliifieid PRegEn 2021-07-18 03:35:38 -04:00
David Harris
a5a7be3e03 Removed EndWalk signal and simplified TLBMissReg 2021-07-18 03:26:43 -04:00
Ross Thompson
d0ed6e250a Fixed LRSC in 64bit version. 32bit version is broken. 2021-07-17 20:58:49 -05:00
David Harris
3be88117c5 added lrsc.sv 2021-07-17 21:15:08 -04:00
David Harris
c29a2ff8df Started atomics 2021-07-17 21:11:41 -04:00
David Harris
3783b5dc00 moved subwordread to lsu 2021-07-17 20:37:20 -04:00
David Harris
84f579038c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-07-17 20:01:23 -04:00
David Harris
d441d4270c LSU cleanup 2021-07-17 20:01:03 -04:00
David Harris
f21582906f Pushing HPTWPAdrM flop into LSUArb 2021-07-17 19:39:18 -04:00
David Harris
989bb7c01b Simplified VPN case statement 2021-07-17 19:34:01 -04:00
Ross Thompson
379cf6c188 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-07-17 18:27:44 -05:00
David Harris
25450bd7c1 Finished HPTW TranslationPAdr simlification 2021-07-17 19:27:24 -04:00
Ross Thompson
053e9593af Before returning to the ready state the dcache must set SelAdr = 0 on the cycle before. 2021-07-17 18:26:29 -05:00
David Harris
217bf37668 Further TranslationVAdr simplification 2021-07-17 19:24:37 -04:00
David Harris
d8397b5e8b Continued Translation Address Cleanup of TranslationPAdrMux 2021-07-17 19:16:56 -04:00
David Harris
6f73844427 Continued Translation Address Cleanup 2021-07-17 19:09:13 -04:00
David Harris
2e2e948023 Refining address interface between HPTW and LSU 2021-07-17 19:02:18 -04:00
David Harris
12cfe91362 Fixed bad register in I-FSD-01 Imperas test. 2021-07-17 17:08:07 -04:00
David Harris
e3bf8db80b trap.sv comment cleanup 2021-07-17 16:01:07 -04:00
David Harris
b2c2194478 trap.sv cleanup 2021-07-17 15:57:10 -04:00
David Harris
777e983c19 Finished removing PageTableEntry redundant signals from hptw 2021-07-17 15:50:52 -04:00
David Harris
348e69c096 hptw: Removed NonBusTrapM from LSU 2021-07-17 15:24:26 -04:00
David Harris
49ec45d04d hptw: Removed NonBusTrapM from LSU 2021-07-17 15:22:24 -04:00
David Harris
e55546da34 hptw: Propagating PageTableEntryF removal through IFU 2021-07-17 15:04:39 -04:00
David Harris
bf56000f4e hptw: Propagating PageTableEntryF removal through LSU 2021-07-17 15:01:01 -04:00
David Harris
d6b8a5e595 hptw: Unified PageTableEntryM and PageTableEntryF outputs of pagetablewalker into PTE 2021-07-17 14:48:44 -04:00
David Harris
ef03ec275c hptw: Added ValidLeaf and ValidNonLeaf for readability, renamed _WDV to _READ states 2021-07-17 14:36:27 -04:00
David Harris
d19679f213 hptw: Eliminated A and D bit faults while walking page table, per spec 2021-07-17 14:29:20 -04:00
David Harris
ad44835e6e hptw: Simplified TranslationVAdr calculation based just on DTLBWalk 2021-07-17 14:16:33 -04:00
David Harris
af02437c3a hptw: renamed DTLBMissQ to DTLBWalk 2021-07-17 14:13:00 -04:00
David Harris
8e966b37f2 hptw: renamed ADRE to ADR 2021-07-17 14:02:59 -04:00
David Harris
95d49e4e9b hptw: replaced PreviousWalkerState with a PageType FSM 2021-07-17 13:54:58 -04:00
David Harris
964f0d9f53 hptw: removed ITLBMissFQ 2021-07-17 13:44:08 -04:00
David Harris
9741b01465 hptw: minor cleanup 2021-07-17 13:40:12 -04:00
David Harris
ee784c19a5 hptw: Simplifed out AnyTLBMiss 2021-07-17 12:07:51 -04:00
David Harris
40989c4e3d hptw: Renamed Memstore to MemWrite 2021-07-17 12:01:43 -04:00
David Harris
ddd9110f7b hptw: Merged RV32/64 FSMs 2021-07-17 11:55:24 -04:00
David Harris
36a8d23222 hptw: FSM simplification 2021-07-17 11:41:43 -04:00
David Harris
6d28f3fe08 hptw: default state should be unreachable 2021-07-17 11:33:16 -04:00
David Harris
ef83a44c4d hptw: factored Misaligned 2021-07-17 11:31:16 -04:00
David Harris
e3b26b7b23 hptw: factored HPTWRead 2021-07-17 11:25:59 -04:00
David Harris
1bbc932bfd hptw: factored HPTWRead 2021-07-17 11:25:52 -04:00
David Harris
37cc2ca30f hptw: factored pregen 2021-07-17 11:11:10 -04:00
David Harris
1595e4f992 HPTW: more cleanup 2021-07-17 04:55:01 -04:00
David Harris
b74f3b14ec HPTW: factored out DTLBWrite/ITLBWrite 2021-07-17 04:44:23 -04:00
David Harris
9775294a6f HPTW: factored out PageTableENtry 2021-07-17 04:40:01 -04:00
David Harris
f168bd6749 more cleaning up FSM 2021-07-17 04:35:51 -04:00
David Harris
e2600bc55d cleaning up FSM 2021-07-17 04:26:41 -04:00
David Harris
52a7dd9ac0 Simplify FSM 2021-07-17 04:12:31 -04:00
David Harris
31a3b39e5c Pulled TranslationPAdr mux out of HPTW FSM 2021-07-17 04:06:26 -04:00
David Harris
7eb03c2ff6 Simplified bad PTE detection 2021-07-17 03:30:17 -04:00
David Harris
b8ee8a8ce0 Pulled out shared PTEReg 2021-07-17 03:21:09 -04:00