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115 Commits

Author SHA1 Message Date
David Harris
dc3284049c Rolled back B extension in rv32/64gc MISA because imperasDV isn't matching 2023-12-21 11:03:50 -08:00
David Harris
09ea6e6485 Set B in MISA for rv32gc and rv64gc 2023-12-20 16:29:31 -08:00
Rose Thompson
5062a8c89c Added parameter for cache's SRAM length. 
Progress towards verilator support.
 2023-12-18 12:50:49 -06:00
Rose Thompson
b02bd6c835 Finally we got the wally tracer working with linux. 2023-11-21 13:45:55 -06:00
Rose Thompson
b137759b45 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-11-20 10:34:36 -06:00
Rose Thompson
3594c08d4b Modified linux imperas tests to 
1. enable zicclsm
2. enable logging at 7000 ms
 2023-11-20 10:30:35 -06:00
David Harris
b692c913c4 Changed rv32gc to do IDIV in MDU and have k=2 copies of FDIV stages; added correct sky130 adder data; fixed feature substitution in synthesis makefile 2023-11-18 20:56:50 -08:00
David Harris
acc2db256f turn off IDIVONFPU when FSUPPORTED=0. Already checked in sim, but need it in synth too for feature sweep 2023-11-17 20:25:24 -08:00
David Harris
96556064a4 Restored RV64GC BPRED_SIZE=10 for consistent synthesis results 2023-11-17 18:31:44 -08:00
David Harris
fb135c957c Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-11-14 15:19:22 -08:00
David Harris
5e9157244b Restored Zfh to 0 for rv64gc because it breaks floating-point tests 2023-11-14 15:18:16 -08:00
Rose Thompson
bf51948616 Merge pull request #474 from davidharrishmc/dev 
FP and synthesis cleanup
 2023-11-14 12:03:01 -08:00
David Harris
8ba0336c6f Removed unused addins, cleaned up configuration to support half precision on RV64gc, gate unused hazard inputs to reduce critical path in rv32e 2023-11-14 11:01:58 -08:00
David Harris
5211b3aa85 Merge pull request #473 from ross144/main 
Missed a few files in the last pull request.  Removes the fpga config from the linter.
 2023-11-14 10:15:31 -08:00
Rose Thompson
fdb75203cb Added cbop to to rv32gc. 2023-11-14 10:55:22 -06:00
David Harris
a77bea9954 Merge pull request #472 from ross144/main 
Merge Zicclsm into main branch and removes the FPGA config.  FPGA makefile now automatically creates the config when building
 2023-11-14 08:34:06 -08:00
Rose Thompson
05eb5460b4 Removed fpga config. No longer needed. 2023-11-13 17:50:29 -06:00
Rose Thompson
95fc5f4a1c Towards removing the FPGA config file. 2023-11-13 17:20:26 -06:00
David Harris
571c7d3be4 Divider cleanup 2023-11-12 19:41:12 -08:00
David Harris
f437336540 Explained sqrt preshifting 2023-11-12 10:05:54 -08:00
David Harris
6ac83c776e Cleaned up number of bits in fdivsqrt 2023-11-11 15:50:06 -08:00
David Harris
2bf5143163 Bug fixes related to size of fpdivsqrt bit count and number of cycles 2023-11-11 05:58:53 -08:00
David Harris
448ced00c5 Fixed testbench-fp to reflect signal name changes 2023-11-11 04:05:34 -08:00
David Harris
d5ba8fc5e6 fdivsqrt parameter cleanup 2023-11-10 18:33:08 -08:00
David Harris
3cae2385ab Simplified out LOGRK parameter 2023-11-10 18:19:41 -08:00
Rose Thompson
b74bfbeefd Merge branch 'main' into Zicclsm 2023-11-10 16:15:32 -06:00
David Harris
953c53d065 fdivsqrt parameter cleanup 2023-11-10 09:11:15 -08:00
David Harris
4c106215f4 Started cleaning up shifting leading 1 in fdivsqrt 2023-11-10 08:46:55 -08:00
Rose Thompson
0a4ed5515b Merge branch 'main' into Zicclsm 2023-11-02 12:55:51 -05:00
Rose Thompson
7222aaa196 Enabled Zicclsm in rv64gc. 2023-11-02 12:47:40 -05:00
naichewa
e3d8162279 harris code review 3 2023-11-01 10:14:15 -07:00
naichewa
7dd3f24d6c Merge branch 'main' into spi 2023-10-30 17:01:41 -07:00
David Harris
f6a7f707bd Fixed test cases for medeleg issue 444. Also added a COMPRESSED_SUPPORTED parameter true when C or Zca is supported, and use this to get compressed hardware such as the spill logic and the +2 adder. 2023-10-30 09:56:17 -07:00
Rose Thompson
657409aec5 Addec ZICCLSM to config files and started on lsu instance. 2023-10-27 13:07:23 -05:00
David Harris
b76c371e45 Config file cleanup 2023-10-18 05:38:36 -07:00
naichewa
0ff9ce527d Merge branch 'main' into spi 2023-10-16 22:59:50 -07:00
David Harris
1a6e57f8c0 Renamed wally-config to config in many comments 2023-10-16 13:49:09 -07:00
naichewa
d5d4f9d044 transferred spi changes in ECA-authorized commit 2023-10-12 13:36:57 -07:00
David Harris
28752303be Added ZCA/ZCF/ZCD/ZCB support. Doesn't break regression, but not tested. Need to get tests for Zcb. Draft tests are in riscv-arch-test but not yet committed there 2023-10-04 12:28:12 -07:00
Ross Thompson
f863cbf366 Actually fixed non-power of 2 issue with RAS. 
Added RAS swapping to branch predictor scripts and configurations.
 2023-09-27 12:25:05 -05:00
Ross Thompson
95c653e7df Fixes the bpred-sim.py to support command line parameterization of the branch predictor while using the new parameterization. This is definitely a hack, but I don't see a better way. 2023-09-15 14:05:26 -05:00
Kevin Kim
dabd15e029 synth works 2023-08-26 21:11:21 -07:00
David Harris
7a092a2275 Fixed merge conflict for ZICBOP 2023-08-25 18:41:57 -07:00
David Harris
f7b50f4721 Preparing to merge with CBO* changes 2023-08-25 18:41:03 -07:00
David Harris
c6631ef808 Added N and PBMT bits to MMU PTE 2023-08-24 19:44:46 -07:00
Ross Thompson
914b6f9734 Now have CBOZ instructions working! 2023-08-24 16:47:35 -05:00
Ross Thompson
0662df511d Modified rv32gc and rv64gc configs to enabled Zicbom. 2023-08-21 13:48:20 -05:00
David Harris
d58ece3d44 renamed test-shared.vh to config-shared.vh 2023-07-30 05:22:39 -07:00
Ross Thompson
dbf9e5da0b Updated Arty A7 fpga config and device tree to 256MiB main memory. 2023-07-25 15:11:47 -05:00
Ross Thompson
0ae9e8bfde Removed old sdc from all configs. 2023-07-24 15:55:22 -05:00