David Harris
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cfecd48752
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Merge pull request #338 from ross144/main
First pass at testbench restructuring
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2023-06-15 14:36:28 -07:00 |
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Ross Thompson
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110a41c046
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Have the linux testbench working in the mean time. Before the consolidation.
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2023-06-15 16:18:37 -05:00 |
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Ross Thompson
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6d31936e89
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Added comment to uart LCR to check reset value after updating FPGA.
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2023-06-15 15:39:51 -05:00 |
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Ross Thompson
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34d1d50b87
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-06-15 15:38:38 -05:00 |
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Ross Thompson
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a011b7d591
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Merge branch 'testbench-params2'
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2023-06-15 15:31:13 -05:00 |
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Ross Thompson
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7278e0b2cc
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Merge pull request #333 from davidharrishmc/dev
cvw.sv moved to root to avoid warnings; UART cleanup and QEMU removal
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2023-06-15 16:28:21 -04:00 |
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Ross Thompson
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a55bcad5c1
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-06-15 14:57:23 -05:00 |
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Ross Thompson
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3c4677ef63
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Major cleanup of testbench.
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2023-06-15 14:57:05 -05:00 |
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David Harris
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52ab586a9d
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Added input gating on FPU
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2023-06-15 12:38:33 -07:00 |
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David Harris
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524d8e8469
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Gated MDU to save power; doesn't seem to have affected simulation time
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2023-06-15 12:17:23 -07:00 |
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David Harris
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c7d06382b3
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Bit manipulation comment cleanup
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2023-06-15 12:16:46 -07:00 |
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Ross Thompson
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e3cf1419ed
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Deleted remaining old configs except fpga as I still need to create the parameterized version.
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2023-06-15 14:08:13 -05:00 |
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Ross Thompson
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44c72c20e2
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Actually removed old `define configuration file for rv64gc. There were a lot of dangling problems.
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2023-06-15 14:05:44 -05:00 |
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David Harris
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33ff9766b4
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Gated inputs to BMU when inactive to save power and simulation time
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2023-06-15 11:56:59 -07:00 |
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Ross Thompson
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2fc8080102
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Got the srams parameterized correctly now.
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2023-06-15 13:42:24 -05:00 |
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David Harris
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e0b6a2d693
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Fixed UART merge conflict
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2023-06-15 11:36:37 -07:00 |
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David Harris
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cdee4e9b91
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Merge pull request #337 from harshinisrinath1001/main
Fixed the spacing of the uncore and wally modules
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2023-06-15 11:33:29 -07:00 |
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Ross Thompson
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e431f90cf3
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Found a whole bunch of files still using the old `define configurations.
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2023-06-15 13:09:07 -05:00 |
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Harshini Srinath
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37c930bb27
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Update wallypipelinedsoc.sv
Program clean up
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2023-06-15 10:39:37 -07:00 |
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Harshini Srinath
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fd00067b7f
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Update wallypipelinedcore.sv
Program clean up
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2023-06-15 10:38:38 -07:00 |
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Harshini Srinath
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e3f8280ff9
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Update cvw.sv
Program clean up
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2023-06-15 10:29:33 -07:00 |
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Harshini Srinath
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e9cfbd95f4
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Update uncore.sv
Program clean up
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2023-06-15 10:23:47 -07:00 |
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Harshini Srinath
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5d8e120031
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Update uart_apb.sv
Program clean up
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2023-06-15 10:21:46 -07:00 |
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Harshini Srinath
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53ad51ae54
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Update uartPC16550D.sv
Program clean up
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2023-06-15 10:20:29 -07:00 |
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Harshini Srinath
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ae165b35f9
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Update rom_ahb.sv
Program clean up
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2023-06-15 10:13:15 -07:00 |
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Harshini Srinath
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97917c2a44
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Update ram_ahb.sv
Program clean up
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2023-06-15 10:10:38 -07:00 |
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Harshini Srinath
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a9495e8595
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Update plic_apb.sv
Program clean up
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2023-06-15 10:08:16 -07:00 |
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Harshini Srinath
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afa0bcdd16
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Update gpio_apb.sv
Program clean up
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2023-06-15 10:04:28 -07:00 |
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Harshini Srinath
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83acb77507
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Update clint_apb.sv
Program clean up
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2023-06-15 09:59:11 -07:00 |
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David Harris
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bcb9c242d4
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Added BMU instructions to instruction name decoder
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2023-06-15 09:26:09 -07:00 |
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David Harris
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302238c3aa
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Fixed cvw path in lint-wally
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2023-06-15 07:02:59 -07:00 |
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David Harris
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380c9e1dde
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-06-15 07:01:44 -07:00 |
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David Harris
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010ff382c2
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Merge pull request #332 from harshinisrinath1001/main
Fixed spacing for generic, ieu, ifu, lsu, mdu, mmu, and privileged modules and deleted CodeAligner.py
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2023-06-15 07:00:47 -07:00 |
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Ross Thompson
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d79c084a70
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Significant refactoring of testbench.
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2023-06-14 17:02:49 -05:00 |
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Ross Thompson
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7ac5239d6a
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Removed old configs from function name module.
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2023-06-14 16:35:55 -05:00 |
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Ross Thompson
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6bb5f32eb9
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Improved simulation speed by gating bitmanip zbc's clmul's X and Y inputs with BSelect != 11. Reduced simulation time from 3m45s to 2m35s.
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2023-06-14 15:28:58 -05:00 |
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Ross Thompson
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19b7819d53
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Found and fixed the source of the new testbench slow down. I accidentally increased the size of the signature buffer by 10x.
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2023-06-14 14:11:25 -05:00 |
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Harshini Srinath
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e0a30ecc22
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Merge branch 'main' into main
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2023-06-14 11:52:45 -07:00 |
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Ross Thompson
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7fb58f5cac
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more testbench improvements.
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2023-06-14 12:23:26 -05:00 |
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Ross Thompson
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8caa4dfcfb
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Continued improvements to testbench.
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2023-06-14 12:11:55 -05:00 |
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Ross Thompson
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005307fc16
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Resolved the duplicated check signature issue.
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2023-06-14 11:50:12 -05:00 |
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David Harris
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fe35f9ecdb
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Moved cvw.sv to src root directory to avoid double-compiling and producing a warning. Adjusted to files to reflect this.
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2023-06-14 09:44:52 -07:00 |
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Ross Thompson
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c91530aa17
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Updates to wave file.
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2023-06-14 10:49:09 -05:00 |
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David Harris
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59bf356064
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Removed *** from UART code
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2023-06-14 08:47:01 -07:00 |
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David Harris
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ea805d32ec
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Removed QEMU from UART
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2023-06-14 08:39:01 -07:00 |
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Harshini Srinath
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629ccb191f
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Update csrs.sv
Program clean up
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2023-06-13 22:16:43 -07:00 |
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Harshini Srinath
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49c84f888f
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Update csrm.sv
Program clean up
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2023-06-13 22:08:06 -07:00 |
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Harshini Srinath
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23eeda6370
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Update csrc.sv
Program clean up
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2023-06-13 21:59:02 -07:00 |
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Harshini Srinath
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aff15a0a46
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Update csrc.sv
Program clean up
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2023-06-13 21:54:47 -07:00 |
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Harshini Srinath
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fb019a736c
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Update csr.sv
Program clean up
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2023-06-13 21:12:49 -07:00 |
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