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Author SHA1 Message Date
David Harris
b34d2065c3 LZA cleanup 2022-08-01 12:30:42 -07:00
David Harris
99462049e7 LZA refactoring switched to Pp1, Gm1, Km1 2022-08-01 12:20:23 -07:00
David Harris
3c08aabcd3 LZA refactoring 2022-08-01 11:36:21 -07:00
David Harris
7f9b601467 fmalza edits to match textbook 2022-08-01 18:23:39 +00:00
David Harris
257107f908 Partitioned fma into separate files 2022-08-01 18:07:38 +00:00
David Harris
93d7d7179e Added parity and stop bit tests to UART 2022-07-28 04:35:51 +00:00
David Harris
429bdae1c4 Fixed UART reference output 2022-07-27 22:16:38 +00:00
David Harris
b08c87cb47 Finished UART test 2022-07-27 04:06:59 +00:00
David Harris
75a265159b Increased timeout threshold to avoid timeout building riscof tests on slow machine 2022-07-27 04:05:21 +00:00
slmnemo
7348af7fd5 Updated reference file for UART test 2022-07-26 09:39:31 -07:00
slmnemo
a9d5805990 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-26 09:15:20 -07:00
slmnemo
5218865a7f Committing changes made to UART test 2022-07-26 09:14:40 -07:00
David Harris
9ecef0c4cd fixed testbench merge comflict 2022-07-26 06:21:46 -07:00
David Harris
2d7f4b133c More work toward riscof tests 2022-07-26 06:19:13 -07:00
David Harris
766252db1b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally 2022-07-25 23:29:08 +00:00
David Harris
5c54c5b521 Added rv32f tests to RV64gc 2022-07-25 23:29:05 +00:00
David Harris
c6a58eb5b6 Tests making successfully except for rv32gc_arch32f, which has FLEN=64 and tries using fld/fsd 2022-07-25 16:23:10 -07:00
David Harris
416f5edfe0 More riscof makefile tuning 2022-07-25 21:15:56 +00:00
David Harris
7f7b3359b0 Cleaning up Makefiles for riscof to run each set of tests individually and eliminate warnings 2022-07-25 20:50:38 +00:00
David Harris
62be9963d8 Fixed synthesis by removing wally-config.vh at level above hdl directory 2022-07-25 01:50:38 +00:00
Ross Thompson
8193946996 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-23 08:41:59 -05:00
Ross Thompson
05484c4c05 signal name cleanup. 2022-07-22 23:36:27 -05:00
Ross Thompson
27e32980ad cache cleanup after removing replay on cpubusy. 2022-07-22 23:30:25 -05:00
Ross Thompson
17ae1a1b1b cache fsm cleanup after removal of replay. 2022-07-22 23:25:09 -05:00
Ross Thompson
abc79c6c8e Possible improvement to cache which removes the cpu_busy states. 2022-07-22 23:20:37 -05:00
Katherine Parry
655e2d3810 merged radix-2 sqrt into divider - doesnt work yet 2022-07-23 00:41:18 +00:00
slmnemo
bfced6bfe8 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-22 17:13:38 -07:00
slmnemo
ca4511b6dc Fixed UART FIFO bugs and added FIFO tests 2022-07-22 17:13:19 -07:00
Daniel Torres
d0aaae26fe fixed wally rv32e tests, updated regression makefile to new testflow 2022-07-22 17:09:46 -07:00
Daniel Torres
35878755f5 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-22 15:35:25 -07:00
Daniel Torres
4da96c5791 fixed 32priv tests, now passing 2022-07-22 15:35:20 -07:00
Katherine Parry
b3d932cd61 divider sizes reworked to match book 2022-07-22 22:02:04 +00:00
Daniel Torres
24828db612 changes to test.vh for compatability 2022-07-22 15:00:48 -07:00
Daniel Torres
4198145ce2 added changes to stvec of reference signatures, modified some tests to copy over reference file instead of running on sail 2022-07-22 14:58:55 -07:00
slmnemo
ba2dcf6da4 fixed error in tests.vh 2022-07-22 14:55:55 -07:00
slmnemo
ec1ed5bd94 Added UART test to peripheral test 2022-07-22 14:55:34 -07:00
slmnemo
141f2a40e4 UART updates and PMA fix 2022-07-22 14:49:03 -07:00
Daniel Torres
574e603d69 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-22 13:52:19 -07:00
Daniel Torres
139e657fcc commented out embench test that should be commented out 2022-07-22 13:52:13 -07:00
slmnemo
df411497e0 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-07-22 12:36:06 -07:00
slmnemo
9cca567136 Added test comments to reference output 2022-07-22 12:35:59 -07:00
slmnemo
cb16a75119 Added PLIC test to regression 2022-07-22 12:35:37 -07:00
Daniel Torres
0e75142ef4 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-22 11:16:09 -07:00
Daniel Torres
95fdd408ee commiting current changes to riscof wally tests 2022-07-22 11:14:04 -07:00
cturek
e2691c02b7 Square root negative exponent handling 2022-07-22 16:45:19 +00:00
slmnemo
d38369e8bf Added new PLIC and UART tests 2022-07-22 07:12:55 -07:00
slmnemo
df568fd202 Added PLIC and UART tests and new functions to the test library 2022-07-22 07:10:39 -07:00
David Harris
d22587090b Reset MSR on read 2022-07-22 04:29:27 +00:00
Daniel Torres
c29a60c198 changed gitignore, updated version of arch tests on main build 2022-07-21 21:10:15 -07:00
Daniel Torres
ae0f8de2b5 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-07-21 20:59:01 -07:00