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Configurable RISC-V Processor
1,015 Commits 5 Branches 2 Tags 53 MiB
SystemVerilog 33.7%
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C 5.8%
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72d8d34e3c
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David Harris 72d8d34e3c allow all size memory access in CLINT; added underscore to peripheral address symbols
2021-06-18 08:05:50 -04:00
riscv-coremark Commit message 2021-06-17 14:49:13 -04:00
sky130 sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
testsBP Added special tests for checking the accuracy of global and gshare branch 2021-06-04 11:01:54 -05:00
wally-pipelined allow all size memory access in CLINT; added underscore to peripheral address symbols 2021-06-18 08:05:50 -04:00
.gitattributes moved shared constants to a shared directory 2021-06-03 22:41:30 -04:00
.gitignore still not sure if QEMU workaround is correct, but here is all linux progress so far 2021-06-17 00:50:02 -04:00
.gitmodules sky130 18T and 15T cell libraries removed 2021-02-14 09:05:41 -06:00
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README.md

README.md

riscv-wally

Configurable RISC-V Processor