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Author SHA1 Message Date
David Harris
b085339303 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-20 21:16:25 -08:00
David Harris
07810f4025 Renamed to setup.sh and fixed path bug 2021-12-20 21:14:35 -08:00
David Harris
e00791a890 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-21 05:10:17 +00:00
David Harris
09a24f7240 Improving Wally installation makefile 2021-12-21 05:10:14 +00:00
David Harris
bf9082b0ad Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-20 21:09:20 -08:00
David Harris
475fa01767 Fixing paths in wally-setup.sh 2021-12-20 21:08:34 -08:00
Ross Thompson
6acf6257e4 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-20 21:26:48 -06:00
Ross Thompson
50b307bc0e Looks like rdtime was accidentally replaced with rrame from a find and replace. 2021-12-20 21:26:38 -06:00
David Harris
972841717f Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-21 02:35:45 +00:00
David Harris
787af4287e Removed riscv-isa-sim submodule from Wally; use it in /opt/riscv instead 2021-12-21 02:35:41 +00:00
Ross Thompson
8416cae3fe Fixed Type 5b interaction between dcache and hptw. 
This is a load concurrent with ITLBMiss.
 2021-12-20 18:33:31 -06:00
Ross Thompson
b6d75d453a Modified LSU verilog is compatible with vivado. have to use extra logic IEUAdrExtM. 2021-12-20 10:03:56 -06:00
Ross Thompson
beb1988539 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-20 10:03:19 -06:00
Ross Thompson
df8bd78679 More signal name cleanup in LSU. 2021-12-19 22:47:48 -06:00
Ross Thompson
3eb5f33705 Remove verbosity from lsu state machine. 2021-12-19 22:41:34 -06:00
Ross Thompson
d3c3422d12 Rename of SelPTW to SelHPTW. 2021-12-19 22:24:07 -06:00
Ross Thompson
8feb36b926 Signal renames. 2021-12-19 22:21:03 -06:00
Ross Thompson
dc82d44f9e Hardware reductions in the lsu. 2021-12-19 22:00:28 -06:00
Ross Thompson
dc95896303 Removed HPTWStall. Not needed as InterlockStall from the LSU provides the equivalent. 2021-12-19 21:36:54 -06:00
Ross Thompson
138da1fefa Removed lsuArb and placed remaining logic in lsu.sv. 
Removed after itlb walk signal as the dcache no longer has any need for this.
Formated lsu.sv
 2021-12-19 21:34:40 -06:00
Ross Thompson
cc5c5da8bc Added file showing how to compile riscv toolchain for different extension combinations. 2021-12-19 20:31:55 -06:00
Ross Thompson
596cc4fde4 Moved convert2bin.py to the tests directory. This file converts the qemu ram.txt output into a binary for copy to flash card. 
mv qemu patches to tests directory.
 2021-12-19 20:11:32 -06:00
David Harris
a25d541dcf Moved generate of conditional units to hart 2021-12-19 17:03:57 -08:00
David Harris
3c3bfd055e Moved generate statements for optional units into wallypipelinedhart 2021-12-19 16:53:41 -08:00
Ross Thompson
d9cc9afd49 Changes to buildroot to support MemAdrM to IEUAdrM name changes. 2021-12-19 18:24:40 -06:00
Ross Thompson
32a4afc7a1 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-19 18:16:49 -06:00
Ross Thompson
a39b47d226 Switched to using an always block for lsu stall logic. This avoids the problematic x propagation. 2021-12-19 18:16:08 -06:00
Ross Thompson
eceb418056 Implemented what I think is the last required change for the lsu state machine. 2021-12-19 17:57:12 -06:00
Ross Thompson
fe5c05eb8d Created hack to get around imperas64mmu unknown (value = x) bug. 2021-12-19 17:53:13 -06:00
Ross Thompson
c453b285dc Fixed bug where icache did not replay PCF on itlb miss. 2021-12-19 17:01:13 -06:00
Ross Thompson
c9291655da Fixed bug most of the bugs related to the dcache changes, but the mmu tests don't pass. 2021-12-19 16:12:31 -06:00
David Harris
53cd2ac049 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-19 13:53:53 -08:00
David Harris
9e6c9c38c0 ALUControl cleanup 2021-12-19 13:53:45 -08:00
Katherine Parry
e3f2a252cd fixed some small errors in FMA 2021-12-19 13:51:46 -08:00
Ross Thompson
f4d778c2f6 Corrected the LSU's fsm for stalling CPU. Removed state from hptw fsm. 2021-12-19 15:10:33 -06:00
Ross Thompson
a445bedcd2 Modified the icache memory to read using the virtual (non physical) address in the PCNextF stage. 
This allows recovering from an ITLBMiss to be 1 cycle after and simplifies the hptw slightly.
 2021-12-19 14:57:42 -06:00
Ross Thompson
225cd5a114 Renamed MemAdrM to IEUAdrM. This will free the name MemAdrm for use in the DCache. 2021-12-19 14:00:30 -06:00
Ross Thompson
cd3c1032b7 Adds FSM to LSU which will handle the interactions between the hptw and dcache. This will dramatically simplify the dcache by removing all walker states. 2021-12-19 13:55:57 -06:00
Ross Thompson
1126135b80 minro change. comments about needed changes in dcache. 2021-12-19 13:53:02 -06:00
David Harris
f201af4bb7 Renamed zero to eq in flag generation 2021-12-19 11:49:15 -08:00
David Harris
406f129bed Controller fix 2021-12-18 22:08:23 -08:00
David Harris
67577d7c91 Renamed RD1D to R1D, etc. 2021-12-18 21:26:00 -08:00
David Harris
721d0b5bcf Simplified shifter right input 2021-12-18 10:25:40 -08:00
Ross Thompson
4daeb6657f Merge branch 'tlb_fixes' into main 2021-12-18 12:24:17 -06:00
David Harris
7e026f3e78 Simplified Shifter Right input 2021-12-18 10:21:17 -08:00
David Harris
27ec8ff893 Shared ALU mux input for shifts 2021-12-18 10:08:52 -08:00
David Harris
eed2765033 Factored out common parts of shifter 2021-12-18 10:01:12 -08:00
David Harris
53baf3e787 Cleaning shifter 2021-12-18 09:43:09 -08:00
David Harris
ebcffcdebd Moved W64 truncation after result mux 2021-12-18 09:27:25 -08:00
David Harris
23c6b6370f Forwarding logic factoring 2021-12-18 05:40:38 -08:00