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108 Commits

Author SHA1 Message Date
David Harris
45e5e694ec Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-11-03 16:04:10 -07:00
David Harris
0b35c2ea56 Updated testbenches to capture InstrM because it may be optimized out of IFU 2023-11-03 05:24:15 -07:00
naichewa
b59abc2dcc correct exclusion tags and reset testbench 2023-11-01 10:34:39 -07:00
naichewa
8027a71e86 harris code review 3 2023-11-01 10:14:15 -07:00
naichewa
7a0fb9a193 hardware interlock 2023-10-30 17:00:20 -07:00
naichewa
19e45a9182 Merge branch 'main' into spi 2023-10-16 22:59:50 -07:00
naichewa
95daef38d1 sync fifo passes 2023-10-16 22:57:02 -07:00
David Harris
8dd1617409 Merged testbench 2023-10-16 13:52:24 -07:00
David Harris
1e2f1089ca Incorporated new AMO tests from riscv-arch-test 2023-10-16 10:25:45 -07:00
Rose Thompson
63d6b1d1c8 Removed P.FPGA from testbench. 2023-10-13 14:08:17 -05:00
naichewa
1fa4ad90ec transferred spi changes in ECA-authorized commit 2023-10-12 13:36:57 -07:00
Ross Thompson
3eeecd2f27 Merge branch 'boot' into mergeBoot 
Merges Jacob's new sdc controller into wally.
 2023-07-21 17:43:45 -05:00
Ross Thompson
3bf2b35704 Wow. The newest version of Vivado does not like the enums as parameters. 
The solution is simple.  I changed the type to logic [31:0] and defined macros for the branch predictor types as 32 bit integers.
 2023-07-18 15:07:10 -05:00
Ross Thompson
74834bde2c Removed duplicate signal name from testbench. 2023-07-07 16:34:08 -05:00
Ross Thompson
0394f3232f Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-07-06 14:55:43 -05:00
David Harris
4c921fc797 Added logic to warn about x in memory reads. Added cbo instruction names to testbench decoder 2023-07-02 13:29:27 -07:00
Ross Thompson
626a918668 FPGA updates. 2023-06-20 11:11:34 -05:00
Ross Thompson
509aee36ef Modified the testbench to generate the required files for embench scripts. 2023-06-16 12:27:22 -05:00
Ross Thompson
3f628d6bf2 embench testbench no longer crashes. 2023-06-16 11:54:41 -05:00
Ross Thompson
110a41c046 Have the linux testbench working in the mean time. Before the consolidation. 2023-06-15 16:18:37 -05:00
Ross Thompson
a011b7d591 Merge branch 'testbench-params2' 2023-06-15 15:31:13 -05:00
Ross Thompson
3c4677ef63 Major cleanup of testbench. 2023-06-15 14:57:05 -05:00
Ross Thompson
e431f90cf3 Found a whole bunch of files still using the old `define configurations. 2023-06-15 13:09:07 -05:00
Ross Thompson
d79c084a70 Significant refactoring of testbench. 2023-06-14 17:02:49 -05:00
Ross Thompson
7ac5239d6a Removed old configs from function name module. 2023-06-14 16:35:55 -05:00
Ross Thompson
19b7819d53 Found and fixed the source of the new testbench slow down. I accidentally increased the size of the signature buffer by 10x. 2023-06-14 14:11:25 -05:00
Ross Thompson
7fb58f5cac more testbench improvements. 2023-06-14 12:23:26 -05:00
Ross Thompson
8caa4dfcfb Continued improvements to testbench. 2023-06-14 12:11:55 -05:00
Ross Thompson
005307fc16 Resolved the duplicated check signature issue. 2023-06-14 11:50:12 -05:00
Ross Thompson
5d0e86f650 Fixed another issue with the timing of memory resets in the new testbench. 2023-06-13 16:24:38 -05:00
Ross Thompson
ed7d785175 Now have most of the regression tests running again. 2023-06-13 15:09:40 -05:00
Ross Thompson
5b0467b287 Cleaned up testbench more. 2023-06-13 14:05:17 -05:00
Ross Thompson
7d53af9206 Compacted memory resets. 2023-06-13 13:57:58 -05:00
Ross Thompson
269d7b2430 More cleanup. 2023-06-13 13:54:07 -05:00
Ross Thompson
40f7031fe7 Fixed the multliple reads of the same preload memory file. 2023-06-13 13:52:02 -05:00
Ross Thompson
261b34af5d The testbench now at least runs the arch64i in rv64gc config. Still has several issues 
1. need to remove all dead code
2. seems to still be double reading memory files sometimes.
3. batch mode does not work.
 2023-06-13 13:18:46 -05:00
Ross Thompson
d9f7daf5e0 The new testbench is almost working except the shadow copy is not working. 2023-06-12 15:08:23 -05:00
Ross Thompson
80a6170fe1 Progress towards new testbench. 2023-06-12 14:06:17 -05:00
Ross Thompson
9a1042b0b1 This parameterizes the testbench but does not use the verilator updates or the new testbench. 2023-06-12 11:00:30 -05:00
Ross Thompson
987e5a5bf0 Removed comments around commented code for verilator. 2023-06-11 15:30:51 -05:00
Ross Thompson
1bf57e3dd1 Merge branch 'verilator' 2023-06-11 15:28:04 -05:00
Ross Thompson
74ccabdf69 Fixed the garbled output in embench transcript. 2023-06-08 10:43:46 -05:00
Ross Thompson
822e60bd3d Found the coremark performance issue. The testbench was continuously forcing the BTB to all zeros. Once fixed it resolved the performance problem. 2023-06-05 15:42:05 -05:00
Ross Thompson
80cdb02d43 Changes required to make verilator compile wally's testbench to c++. Not actually tested in simulation yet. 2023-05-31 16:51:00 -05:00
Ross Thompson
903f2f9063 Merge branch 'param-lim-merge' 2023-05-26 16:25:35 -05:00
Ross Thompson
6509463f3d Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-05-24 13:00:50 -05:00
Ross Thompson
c5aeb08e5c Trying to figure out why the parameterization slowed down modelsim so much. 2023-05-24 12:44:42 -05:00
Ross Thompson
485508274e
Merge pull request #297 from davidharrishmc/dev 
Verilator testbench changes
 2023-05-22 13:29:54 -04:00
David Harris
533ddf5eb3 Removed force from branch predictor initialization 2023-05-22 09:57:41 -07:00
David Harris
f257259045 Initial testbench cleanup for Verilator 2023-05-22 09:51:46 -07:00