45 Commits

Author	SHA1	Message	Date
David Harris	71f214df20	Moved fdivsqrtexpcalc to its own file	2022-12-26 08:45:43 -08:00
cturek	ba3aca413c	Added A Sign register. Fixed postprocessing logic for postinc and rem calculation.	2022-12-24 06:46:52 +00:00
David Harris	fe5b9081d9	Removed unused signals from FPU	2022-12-23 00:18:39 -08:00
David Harris	93bb8036be	Revert to 98b824	2022-12-22 23:58:14 -08:00
David Harris	a185f563f2	Clean up unused FPU signals	2022-12-22 23:53:09 -08:00
David Harris	74979cdc82	FDIV merge	2022-12-22 23:03:03 -08:00
David Harris	51b92285d3	Removed unused signals in FPU and CSR	2022-12-22 22:59:05 -08:00
cturek	04bc787647	Added negative-result int diviison support in U and UM registers. 13 tests pass!	2022-12-22 16:25:37 +00:00
cturek	c7d0c8823f	Added ForwardedSrcAM to postprocessor. Now passing 8 tests on rv32gc.	2022-12-22 05:44:55 +00:00
cturek	e441f90b32	Renamed signals to E and M stages, forwarded preprocessed n to fsm	2022-12-22 00:43:27 +00:00
Alessandro Maiuolo	13c9f2e4a5	Added NumZeroE, AZeroM, and BZeroM	2022-12-18 20:02:40 -08:00
cturek	9340a5eb49	Added mux for integer special case, renamed signals to match pipelined stage	2022-12-16 18:43:49 +00:00
cturek	9f1aa7ad19	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-12-16 03:41:39 +00:00
David Harris	a8126458f6	Refactored stalls and flushes, including FDIV flush with FlushE	2022-12-15 10:56:18 -08:00
David Harris	643a2e7cf9	Use FPU divider for integer division when F is supported	2022-12-14 17:03:13 -08:00
cturek	482caec42d	Fixed BZero and initU/initUM muxes	2022-12-14 16:44:46 +00:00
cturek	930fcbe956	Fixed D sizing issues across fdivsqrt. Fixed preproc to accept either int or float inputs	2022-12-10 21:56:35 +00:00
Ross Thompson	350fdd944d	Revert "Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider." ... This reverts commit fb221d7b64.	2022-12-04 00:01:58 +00:00
cturek	fb221d7b64	Changed weird D sizing. Better names in preproc. Finalized Int/Float input to divider.	2022-12-02 21:44:29 +00:00
cturek	04ac350a29	Added flops to preproc	2022-12-02 20:31:08 +00:00
David Harris	1b0f878c16	Renamed DivStartE to IFDivStartE	2022-12-02 11:30:49 -08:00
David Harris	db5f3c15a4	FPU divider working with execute stage stall	2022-12-02 11:11:53 -08:00
cturek	bdb9e24a66	Almost done with Int division	2022-11-22 22:22:59 +00:00
David Harris	be9c618c94	Renamed DivBusy to FDivBusyE in FPU	2022-11-16 10:13:27 -08:00
David Harris	128cc86254	Moved DivStartE to fdivsqrtfsm	2022-11-16 10:00:07 -08:00
cturek	6740d77b63	Added Quotient/Remainder calcs to normal termination	2022-11-13 23:44:34 +00:00
cturek	12e3646153	Added flops for n and m, added B=0 signal	2022-11-13 23:02:43 +00:00
cturek	f10700e666	Added A<B signal to fdivsqrt, started postprocessing merge	2022-11-13 22:40:26 +00:00
cturek	4a8661649c	Added integer step counter to fsm	2022-11-11 00:23:25 +00:00
cturek	54f09f3616	Added conditional OTFC swap for simplified int postprocessing	2022-11-06 23:09:09 +00:00
cturek	2cbe2fd70b	Added n, p, and m signals between fdivsqrt submodules. Added w64 and mdue to divsqrt testbench.	2022-11-06 22:08:18 +00:00
cturek	6bc4c1318e	Added new macros for int div preprocessing, added p, n, and rightshiftx logic	2022-11-06 21:53:48 +00:00
cturek	06a9305766	renamed remOp to RemOp	2022-11-03 22:37:25 +00:00
cturek	e37f564e84	Added rem/div operation to postprocessor	2022-11-02 17:49:40 +00:00
cturek	7301fc7f18	small signal cleanup	2022-10-26 18:42:49 +00:00
cturek	ff7d6b2932	Started Integer Preprocessing	2022-10-25 17:48:43 +00:00
amaiuolo	56455bb9ad	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-10-13 22:36:57 +00:00
amaiuolo	1ae48e0edc	added amaiuolo@hmc.edu	2022-10-13 22:36:52 +00:00
David Harris	2aa43848f5	fdivsqrt code cleanup	2022-10-09 03:37:27 -07:00
David Harris	657f16dfd1	Adding start signals for integer divider to fdivsqrt	2022-09-29 16:30:25 -07:00
cturek	e8a869e0e7	Added integer inputs and flags to divsqrt	2022-09-29 23:08:27 +00:00
David Harris	5e1932c649	Added SpecialCaseReg to hold SpecialCase for fdivsqrtpostproc	2022-09-21 04:55:43 -07:00
David Harris	f7d272c315	Gated sticky bit in fdiv with SpecialCase	2022-09-20 20:05:00 -07:00
David Harris	00c15ec472	renamed q to u for unified digit selection	2022-09-20 04:35:14 -07:00
David Harris	653c458241	Moved fpu modules into subdirectories	2022-09-20 04:12:05 -07:00