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Author SHA1 Message Date
Ross Thompson
ac50a36aac LSU and IFU cleanup. 2022-01-28 15:26:06 -06:00
Ross Thompson
2e00186eea Updated wave.do to match the ifu/lsu changes. 2022-01-28 14:37:15 -06:00
Ross Thompson
42d60235f0 Clean up of mmu instances in IFU and LSU. 2022-01-28 14:02:05 -06:00
Ross Thompson
c5e0024e9f Moved spills to own module. 2022-01-28 13:40:35 -06:00
Ross Thompson
06209c417f Cleaned up the InstrMisalignedFault. 2022-01-28 13:19:24 -06:00
Ross Thompson
862bf2faae Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault. 2022-01-27 17:11:27 -06:00
Ross Thompson
d15cb64bdf Relocated the misalignment faults. 2022-01-27 16:03:00 -06:00
David Harris
30cc27e719 IFU cleanup 2022-01-27 17:18:55 +00:00
David Harris
5ab06fef20 IFU cleanup 2022-01-27 16:41:57 +00:00
David Harris
bdd5796f3a Optimized out second adder from IFU for PC+2 2022-01-27 16:06:24 +00:00
David Harris
7f91170bab Comments in LSU code about restructuring 2022-01-27 15:53:59 +00:00
Ross Thompson
b44f57b6b5 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-27 08:45:33 -06:00
Ross Thompson
284d671da3 Increased number of concurrent tests. 2022-01-27 08:45:25 -06:00
David Harris
448acedd8b Set up rv32emc config 2022-01-27 14:37:58 +00:00
David Harris
2b1aa9cada Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-27 14:33:35 +00:00
David Harris
064a02de18 Added synthesis submodules 2022-01-27 14:31:34 +00:00
Ross Thompson
25c8c45a70 Added generated source code for the wally riscv arch tests rv32i_m and rv64i_m. 2022-01-27 08:11:46 -06:00
Ross Thompson
db0a0bd29e BPPredWrongM needs to be 0 when there is no branch predictor. BPPredWRongM is only used when there is an icacheflush. 2022-01-27 07:59:59 -06:00
Ross Thompson
3ebcd35a8c Added colors to regression script to make it easy to pick out success from fail. 2022-01-26 22:40:32 -06:00
Ross Thompson
cc5a9a015b Removed mux in PCNextF logic. Minor IFU improvements. 2022-01-26 22:33:26 -06:00
Ross Thompson
42ef1e22e5 1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU. 
2. Removed the write address delay from simpleram.sv
3. Fixed rv32tim and rv32ic mode to handle missalignment correctly.
4. Added imperas32i and imperas32c to rv32tim mode.
 2022-01-26 18:23:39 -06:00
Ross Thompson
fc86651937 IFU simplifications. 2022-01-26 13:54:59 -06:00
David Harris
b359499820 Adjusted test cases for new GPIO base address 2022-01-26 19:15:48 +00:00
David Harris
748375c82f Updated configs to fix GPIO address to match FU540 2022-01-26 18:16:34 +00:00
David Harris
21bdce63ff Testgen working for Lab 2 2022-01-26 18:01:51 +00:00
David Harris
4d788505f2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-26 17:21:09 +00:00
David Harris
e16982aeb0 New testgen.py 2022-01-26 17:21:02 +00:00
bbracker
676d4c5fa7 a different approach to QEMU: add Wally as a completely new machine 2022-01-26 15:02:24 +00:00
Ross Thompson
840e814e95 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-25 19:21:04 -06:00
Ross Thompson
d46bc94119 Added pin location for reset on VCU118 board. Somehow this was missing and still worked. 2022-01-25 17:48:42 -06:00
David Harris
3a7786877a Removed and restored embench-iot 2022-01-25 22:12:28 +00:00
Ross Thompson
bb11f5637c Added comport.setup to remind how to configure com port for xilinx fpga. 
Added load-deadlock.tsm to trigger load operation deadlock.
 2022-01-25 14:54:38 -06:00
David Harris
8d04e83c9f simpleram simplification 2022-01-25 19:46:13 +00:00
David Harris
9da1ed4ed9 simpleram simplification 2022-01-25 19:40:07 +00:00
David Harris
a86a9f5c2a simpleram simplification 2022-01-25 18:26:31 +00:00
David Harris
e3136c9a1e simpleram address simplification 2022-01-25 18:17:33 +00:00
David Harris
7ad2eb009a simpleram address simplification 2022-01-25 18:00:50 +00:00
David Harris
6a555032eb simpleram clk and reset simplification 2022-01-25 17:34:15 +00:00
David Harris
cf50beb958 Start of IFU cleanup 2022-01-25 17:31:53 +00:00
David Harris
99a824fdc1 removed sum executable 2022-01-25 10:24:05 +00:00
David Harris
8d83b3b722 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-25 06:53:07 +00:00
David Harris
2bc7399ad4 More example Makefile cleanup 2022-01-25 06:53:03 +00:00
davidharrishmc
f6a27588f3 Update README.md 2022-01-24 15:47:42 -08:00
davidharrishmc
544b9273c2 Update README.md 2022-01-24 15:46:24 -08:00
David Harris
2dc73574d3 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-24 23:21:16 +00:00
David Harris
12e08d8055 Fixed sumtest reference output; added embench benchmark directory 2022-01-24 23:21:09 +00:00
kaveh Pezeshki
b0cbe9dba8 added qemu patches in tests/linux-testgen/qemu 2022-01-24 07:52:07 +00:00
Ross Thompson
8ef70389d3 Added spill support back into the IROM IFU. 2022-01-21 15:50:54 -06:00
Ross Thompson
9982549057 Changed the IROM and DTIM memories to behave like edge-triggered srams. 2022-01-21 15:42:54 -06:00
David Harris
0ceaf792ed erge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-21 00:12:18 +00:00