Kevin Kim
aadc1de746
zbs passes lint
2023-02-02 20:04:38 +00:00
Kevin Kim
ae5d7844a9
clmul finished initial hdl; passes lint
2023-02-02 19:49:14 +00:00
Kevin Kim
f07ffbb63b
continued clmul unit
2023-02-02 18:54:33 +00:00
Kevin Kim
bd8f0189ee
started clmul
2023-02-02 16:40:58 +00:00
Kip Macsai-Goren
0281330fe8
Merge remote-tracking branch 'upstream/main' into main
2023-02-01 21:31:57 -08:00
Kip Macsai-Goren
f126d1e0ef
added beginning of a ZBS instruction module to the ALU. Control signals still needed
2023-02-01 21:31:25 -08:00
David Harris
c5578cc2fb
Merge pull request #45 from stineje/main
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Update ram2 and other memories and associated wrappers
2023-02-01 15:06:30 -08:00
James Stine
fc5692629a
Update ram2 and other memories and associated wrappers
2023-02-01 17:03:48 -06:00
David Harris
733b877f1d
Merge pull request #36 from davidharrishmc/dev
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RV32imc configuration
2023-02-01 04:44:36 -08:00
David Harris
ce82d8d550
Fixed merge conflict to get synthesis working again
2023-02-01 04:43:57 -08:00
David Harris
39942bbc45
Merge pull request #43 from mmasserfrye/main
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ram size, bpred size, memories *SYNTH NOT FUNCTIONAL*
2023-02-01 04:13:37 -08:00
Madeleine Masser-Frye
57b35c293d
added memories (not tested)
2023-02-01 06:08:27 +00:00
Madeleine Masser-Frye
a81d569e1a
increased bpred size to (2^) 5
2023-02-01 05:51:31 +00:00
Madeleine Masser-Frye
d734f7af92
updated synth makefile to change all relevant
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ram ranges to 1FF
2023-02-01 05:40:35 +00:00
Madeleine Masser-Frye
fa9a99c8e8
Merge branch 'main' of https://github.com/mmasserfrye/cvw
2023-02-01 05:23:04 +00:00
David Harris
5d7dcfb748
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-01-31 14:40:19 -08:00
David Harris
625ca64474
Removed student solution to fir
2023-01-31 14:40:12 -08:00
David Harris
5e607f7c82
Merge pull request #42 from ross144/main
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Scripts to run imperas
2023-01-31 14:31:10 -08:00
Ross Thompson
7166fcd4d2
Updates to RAS.
2023-01-31 15:17:32 -06:00
Ross Thompson
dd556e8763
Simplified RAS.
2023-01-31 14:54:05 -06:00
Ross Thompson
122809b2b2
RAS file name was spelled wrong.
2023-01-31 14:35:05 -06:00
Ross Thompson
bfbf534830
Created scripts to install imperas and run a single test using imperas.
2023-01-31 13:51:05 -06:00
David Harris
7995872854
Merge pull request #41 from ross144/main
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Merged imperas branch into main. Remove old branch when pull request accepted.
2023-01-31 11:35:50 -08:00
Ross Thompson
7593167678
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-01-31 13:04:41 -06:00
Ross Thompson
eededd1ba9
Fixed remaining bugs in the imperas merge.
2023-01-31 13:04:26 -06:00
Ross Thompson
0678e70b4b
Merge branch 'imperas'
2023-01-31 12:46:22 -06:00
Ross Thompson
52bdf32575
Minor bug fix in gshare.
2023-01-31 10:45:32 -06:00
Ross Thompson
e7b91d5934
Renamed signals in RAS.
2023-01-31 10:44:11 -06:00
David Harris
a8f268e2a4
Removed output delay in synthesis
2023-01-31 04:37:23 -08:00
Ross Thompson
b4854d8e94
Found small bug in gshare.
2023-01-31 00:17:49 -06:00
Ross Thompson
20e99dce73
Fixed parameterization in testbench.
2023-01-31 00:11:01 -06:00
Ross Thompson
b64b3016e2
Parameterized testbench branch predictor preload.
2023-01-31 00:08:11 -06:00
Ross Thompson
22ef051603
More branch predictor cleanup.
2023-01-30 23:55:52 -06:00
Ross Thompson
61759af9dc
Improved signal names.
2023-01-30 23:51:04 -06:00
Ross Thompson
165b4858d7
Major cleanup of branch predictor.
2023-01-30 23:37:34 -06:00
Ross Thompson
57ab5a7488
Simplified gshare.
2023-01-30 19:27:18 -06:00
Ross Thompson
0e29a5f9c2
Minor gshare optimization.
2023-01-30 18:13:12 -06:00
David Harris
6777fd9b55
Restored top-level modules without import statements
2023-01-30 12:54:40 -08:00
David Harris
49e45f45b7
Moved out version of wally using package because synthesis isn't working yet
2023-01-30 12:48:52 -08:00
David Harris
1e7c9f026c
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-01-30 11:00:51 -08:00
David Harris
0c20ac010c
Updated Questa to 2022.4_2.
2023-01-30 11:00:41 -08:00
Madeleine Masser-Frye
fa47313086
Merged conflicts in fixing synthesis config/hdl writing ( #40 )
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* Fixed writing config files for synth sweeps
* cleaned up comments
* Fixed copying hdl subdirectories and referencing the correct config files for modified features
* improved readability for synth scripts
* cleans run directory post run and leaves copy of wally-config
2023-01-30 20:54:19 +02:00
Madeleine Masser-Frye
8f635e42c5
Merge branch 'main' of https://github.com/mmasserfrye/cvw
2023-01-30 18:51:05 +00:00
David Harris
5c3e0c8a4d
Merge pull request #38 from ross144/main
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Imperas found bug with hptw
2023-01-30 10:10:41 -08:00
Ross Thompson
7a4218788c
Imperas found a real bug in virtual memory.
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If the instruction address spilled across two pages and the second page misses the TLB,
the HPTW received a tlb miss at the address of the first page rather than the second.
After the walk the TLB was updated with the PTE from the first page at the address of the
second page.
Example bug
Instruction PCF = 0x2ffe
First page in 0x2ffe and second page in 0x3000.
The second page misses the TLB and generates HPTW request at 0x2ffe rather than 0x3000.
TLB is updated with PTE from 0x2ffe at 0x3000.
2023-01-30 11:47:51 -06:00
Ross Thompson
3190916601
Merge branch 'main' of github.com:ross144/cvw
2023-01-29 22:39:53 -06:00
Ross Thompson
63267ff378
optimized branch predictor by removing unnecessary registers.
2023-01-29 22:39:37 -06:00
Ross Thompson
d78be868c9
Merge branch 'main' of https://github.com/openhwgroup/cvw into main
2023-01-29 22:19:10 -06:00
David Harris
4c75a90e39
Moved WALLY-status-fp-enabled tests from a to priv suites
2023-01-29 17:19:53 -08:00
David Harris
327303e2e2
Moved shared constants into per-processor config and removed wally-constants
2023-01-29 15:55:37 -08:00
