mirror of
https://github.com/openhwgroup/cvw
synced 2025-02-11 06:05:49 +00:00
Merge branch 'main' of https://github.com/mmasserfrye/cvw
This commit is contained in:
Madeleine Masser-Frye
commit
8f635e42c5
5
.gitignore
vendored
5
.gitignore
vendored
@ -129,3 +129,8 @@ tests/custom/crt0/*.a
|
||||
fpga/src/sdc/*
|
||||
fpga/src/sdc.tar.gz
|
||||
fpga/src/CopiedFiles_do_not_add_to_repo/*
|
||||
/pipelined/regression/branch.log
|
||||
/fpga/generator/sim/imp-funcsim.v
|
||||
/fpga/generator/sim/imp-timesim.sdf
|
||||
/fpga/generator/sim/imp-timesim.v
|
||||
/fpga/generator/sim/syn-funcsim.v
|
||||
|
||||
@ -1,48 +0,0 @@
|
||||
Installing Wally, RISC-V tools, and Imperas tests from source gives you maximum control, but has several disadvantages:
|
||||
|
||||
-Building the executables takes several hours.
|
||||
-Linux is poorly standardized, and the build steps might not work on your version
|
||||
-The source files are constantly changing, and the versions you download might not be compatible with this textbook flow.
|
||||
|
||||
Docker is a tools to run applications in a prepackaged container
|
||||
including all of the operating system support required. Wally offers
|
||||
a ~30GB container image with the open-source tools pre-installed from
|
||||
Section D.1. In particular, using the container solves the long build
|
||||
time for gcc and the fussy installation of sail. The container runs on
|
||||
any platform supporting Docker, including Windows and Mac as well as
|
||||
Linux. It can access files outside the container, including local
|
||||
installation of CAD tools such as Questa, and a local clone of the
|
||||
core-v-wally repository.
|
||||
|
||||
Docker can be run on most operating systems, including Linux, Windows,
|
||||
and Mac. The Wally Docker container is hosted at DockerHub
|
||||
(http://docker.io).
|
||||
|
||||
Podman is a more secure and easier-to-use variation of Docker for
|
||||
Linux developed by RedHat. Both Docker and Podman run the same
|
||||
containers.
|
||||
|
||||
This directory has a copy of the file utilized to create the Docker
|
||||
for the toolchain discussed in the text. To build this docker, you can
|
||||
type the following where the last argument is the name where you want
|
||||
to store your docker.
|
||||
|
||||
docker build -t docker.io/wallysoc/wally-docker:latest .
|
||||
|
||||
This can also be changed if you make a mistake by using the tag
|
||||
command. For example, if I wanted to change my docker from
|
||||
wally-docker to wally-docker2, I would type:
|
||||
|
||||
docker tag wallysoc/wally-docker:latest docker.io/wallysoc/wally-docker2:latest
|
||||
|
||||
Once you build your docker, you can run it as given in the Readme.
|
||||
However, you can also push it to DockerHub with the following command.
|
||||
|
||||
docker push docker.io/wallysoc/wally-docker:latest
|
||||
|
||||
To run your docker, you can type the following at a command prompt or
|
||||
terminal.
|
||||
|
||||
docker run -it -p 8080:8080 docker.io/wallysoc/wally-docker
|
||||
|
||||
|
||||
@ -1 +0,0 @@
|
||||
/opt/riscv/imperas-riscv-tests/
|
||||
246
bin/libppa.pl
Executable file
246
bin/libppa.pl
Executable file
@ -0,0 +1,246 @@
|
||||
#!/bin/perl -W
|
||||
|
||||
###########################################
|
||||
## libppa.pl
|
||||
##
|
||||
## Written: David_Harris@hmc.edu
|
||||
## Created: 28 January 2023
|
||||
##
|
||||
## Purpose: Extract PPA information from Liberty files
|
||||
## presently characterizes Skywater 90 and TSMC28hpc+
|
||||
##
|
||||
## The user will need to change $libpath to point to the desired library in your local installation
|
||||
## and for TSMC change the $cellname to the actual name of the inverter.
|
||||
##
|
||||
## A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
##
|
||||
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
##
|
||||
## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
##
|
||||
## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
## except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
## may obtain a copy of the License at
|
||||
##
|
||||
## https:##solderpad.org/licenses/SHL-2.1/
|
||||
##
|
||||
## Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
## either express or implied. See the License for the specific language governing permissions
|
||||
## and limitations under the License.
|
||||
################################################################################################
|
||||
|
||||
use strict;
|
||||
use warnings;
|
||||
|
||||
# global variables for simplicity
|
||||
my @index1; my @index2;
|
||||
my @values;
|
||||
my @cr; my @cf; my @rt; my @ft;
|
||||
|
||||
# cell and corners to analyze
|
||||
my $libpath; my $libbase; my $cellname; my @corners;
|
||||
|
||||
# Sky90
|
||||
$libpath ="/opt/riscv/cad/lib/sky90/sky90_sc/V1.7.4/lib";
|
||||
$libbase = "scc9gena_";
|
||||
$cellname = "scc9gena_inv_1";
|
||||
@corners = ("tt_1.2v_25C", "tt_1.08v_25C", "tt_1.32v_25C", "tt_1.2v_-40C", "tt_1.2v_85C", "tt_1.2v_125C", "ss_1.2v_25C", "ss_1.08v_-40C", "ss_1.08v_25C", "ss_1.08v_125C", "ff_1.2v_25C", "ff_1.32v_-40C", "ff_1.32v_25C", "ff_1.32v_125C");
|
||||
printf("Library $libbase Cell $cellname\n");
|
||||
foreach my $corner (@corners) {
|
||||
&analyzeCell($corner);
|
||||
}
|
||||
|
||||
# TSMC
|
||||
$libpath = "/proj/models/tsmc28/libraries/28nmtsmc/tcbn28hpcplusbwp30p140_190a/TSMCHOME/digital/Front_End/timing_power_noise/NLDM/tcbn28hpcplusbwp30p140_180a";
|
||||
$libbase = "tcbn28hpcplusbwp30p140";
|
||||
$cellname = "INVD1..."; // replace this with the full name of the library cell
|
||||
@corners = ("tt0p9v25c", "tt0p8v25c", "tt1v25c", "tt0p9v85c", "ssg0p9vm40c", "ssg0p9v125c", "ssg0p81vm40c", "ssg0p81v125c", "ffg0p88vm40c", "ffg0p88v125c", "ffg0p99vm40c", "ffg0p99v125c");
|
||||
printf("\nLibrary $libbase Cell $cellname\n");
|
||||
foreach my $corner (@corners) {
|
||||
&analyzeCell($corner);
|
||||
}
|
||||
|
||||
#############
|
||||
# subroutines
|
||||
#############
|
||||
|
||||
sub analyzeCell {
|
||||
my $corner = shift;
|
||||
my $fname = $libpath."/".$libbase.$corner.".lib";
|
||||
open (FILE, $fname) || die("Can't read $fname");
|
||||
my $incell = 0;
|
||||
my $inleakage = 0;
|
||||
my $inpin = 0;
|
||||
my $incellrise = 0;
|
||||
my $incellfall = 0;
|
||||
my $inrisetrans = 0;
|
||||
my $infalltrans = 0;
|
||||
my $inindex = 0;
|
||||
my $invalues = 0;
|
||||
my $searchstring = "cell (".$cellname.")";
|
||||
my $area; my $leakage; my $cap;
|
||||
while (<FILE>) {
|
||||
if (index($_, $searchstring) != -1) { $incell = 1;}
|
||||
elsif ($incell) {
|
||||
if (/cell \(/) {
|
||||
$incell = 0;
|
||||
close(FILE);
|
||||
last;
|
||||
}
|
||||
if (/area\s*:\s*(.*);/) { $area = $1; }
|
||||
if (/cell_leakage_power\s*:\s*(.*);/) { $leakage = $1; $inleakage = 2; }
|
||||
if ($inleakage == 0 && /leakage_power/) { $inleakage = 1; }
|
||||
if ($inleakage == 1 && /value\s*:\s*(.*);/) {
|
||||
$leakage = $1;
|
||||
$inleakage = 2;
|
||||
}
|
||||
if ($inpin == 0 && /pin/) { $inpin = 1; }
|
||||
if ($inpin == 1 && /\s+capacitance\s*:\s*(.*);/) {
|
||||
$cap = $1;
|
||||
$inpin = 2;
|
||||
}
|
||||
if ($inindex == 0 && /index_1/) { $inindex = 1; }
|
||||
if ($inindex == 1) {
|
||||
if (/index_1\s*\(\"(.*)\"\);/) { @index1 = split(/, /, $1); }
|
||||
if (/index_2\s*\(\"(.*)\"\);/) { @index2 = split(/, /, $1); $inindex = 2; }
|
||||
}
|
||||
if ($incellrise == 0 && /cell_rise/) { $incellrise = 1; $invalues = 0;}
|
||||
if ($incellfall == 0 && /cell_fall/) { $incellfall = 1; $invalues = 0; }
|
||||
if ($inrisetrans == 0 && /rise_trans/) { $inrisetrans = 1; $invalues = 0; }
|
||||
if ($infalltrans == 0 && /fall_trans/) { $infalltrans = 1; $invalues = 0; }
|
||||
if ($incellrise == 1 || $incellfall == 1 || $inrisetrans == 1 || $infalltrans == 1) {
|
||||
if (/values/) { $invalues = 1; @values = (); }
|
||||
elsif ($invalues == 1) {
|
||||
if (/\);/) {
|
||||
$invalues = 2;
|
||||
if ($incellrise == 1) { @cr = &parseVals(); $incellrise = 2; }
|
||||
if ($incellfall == 1) { @cf = &parseVals(); $incellfall = 2; }
|
||||
if ($inrisetrans == 1) { @rt = &parseVals(); $inrisetrans = 2; }
|
||||
if ($infalltrans == 1) { @ft = &parseVals(); $infalltrans = 2; }
|
||||
}
|
||||
elsif (/\"(.*)\"/) { push(@values, $1); }
|
||||
}
|
||||
}
|
||||
# print $_;
|
||||
}
|
||||
}
|
||||
|
||||
my $delay = &computeDelay($cap);
|
||||
my $cornerr = sprintf("%20s", $corner);
|
||||
my $delayr = sprintf("%2.1f", $delay*1000);
|
||||
my $leakager = sprintf("%3.1f", $leakage);
|
||||
|
||||
print("$cornerr: Delay $delayr Leakage: $leakager capacitance: $cap\n");
|
||||
#print("$cellname $corner: Area $area Leakage: $leakage capacitance: $cap delay $delay\n");
|
||||
#print(" index1: @index1\n");
|
||||
#print(" index2: @index2\n");
|
||||
#print("Cell Rise\n"); printMatrix(\@cr);
|
||||
#print("Cell Fall\n"); printMatrix(\@cf);
|
||||
#print("Rise Trans\n"); printMatrix(\@rt);
|
||||
#print("Fall Trans\n"); printMatrix(\@ft);
|
||||
}
|
||||
|
||||
sub computeDelay {
|
||||
# relies on cr, cf, rt, ft, index1, index2
|
||||
# index1 for rows of matrix (different trans times, units of ns)
|
||||
# index2 for cols of matrix (different load capacitances, units of pF)
|
||||
|
||||
# first, given true load, create a rise/fall delay and transition
|
||||
# as a function of trans time, interpolated
|
||||
my $cap = shift;
|
||||
my $fo4cap = 4*$cap;
|
||||
my @cri = &interp2(\@cr, $fo4cap);
|
||||
my @cfi = &interp2(\@cf, $fo4cap);
|
||||
my @rti = &interp2(\@rt, $fo4cap);
|
||||
my @fti = &interp2(\@ft, $fo4cap);
|
||||
|
||||
# initially guess second smallest transition time
|
||||
my $tt = $index1[1];
|
||||
# assume falling input with this transition, compute rise delay & trans
|
||||
my $cr0 = &interp1(\@cri, \@index1, $tt);
|
||||
my $rt0 = &interp1(\@rti, \@index1, $tt);
|
||||
# now assuming rising input with rt0, compute fall delay & trans
|
||||
my $cf1 = &interp1(\@cfi, \@index1, $rt0);
|
||||
my $ft1 = &interp1(\@fti, \@index1, $rt0);
|
||||
# now assuming falling input with ft1, compute rise delay & trans
|
||||
my $cr2 = &interp1(\@cri, \@index1, $ft1);
|
||||
my $rt2 = &interp1(\@rti, \@index1, $ft1);
|
||||
# now assuming rising input with rt2, compute fall delay & trans
|
||||
my $cf3 = &interp1(\@cfi, \@index1, $rt2);
|
||||
my $ft3 = &interp1(\@fti, \@index1, $rt2);
|
||||
|
||||
# delay is average of rising and falling
|
||||
my $delay = ($cr2 + $cf3)/2;
|
||||
return $delay;
|
||||
|
||||
# print("tt $tt cr0 $cr0 rt0 $rt0\n");
|
||||
# print("cf1 $cf1 ft1 $ft1 cr2 $cr2 rt2 $rt2 cf3 $cf3 ft3 $ft3 delay $delay\n");
|
||||
}
|
||||
|
||||
sub interp2 {
|
||||
my $matref = shift;
|
||||
my @matrix = @$matref;
|
||||
my $fo4cap = shift;
|
||||
my @interp = ();
|
||||
|
||||
my $i;
|
||||
# interpolate row by row
|
||||
for ($i=0; $i <= $#index1; $i++) {
|
||||
my @row = @{$matrix[$i]};
|
||||
#print ("Extracted row $i = @row\n");
|
||||
$interp[$i] = &interp1(\@row, \@index2, $fo4cap);
|
||||
}
|
||||
return @interp;
|
||||
}
|
||||
|
||||
sub interp1 {
|
||||
my $vecref = shift;
|
||||
my @vec = @$vecref;
|
||||
my $indexref = shift;
|
||||
my @index = @$indexref;
|
||||
my $x = shift;
|
||||
|
||||
# find entry i containing the first index greater than x
|
||||
my $i = 0;
|
||||
while ($index[$i] < $x) {$i++}
|
||||
my $start = $index[$i-1];
|
||||
my $end = $index[$i];
|
||||
my $fract = ($x-$start)/($end-$start);
|
||||
my $interp = $vec[$i-1] + ($vec[$i] - $vec[$i-1])*$fract;
|
||||
|
||||
# print ("Interpolating $x as $interp from i $i start $start end $end based on index @index and vec @vec\n");
|
||||
|
||||
return $interp;
|
||||
}
|
||||
|
||||
sub parseVals {
|
||||
# relies on global variables @values, @index1, @index2
|
||||
my @vals;
|
||||
my $i; my $j;
|
||||
for ($i=0; $i <= $#index1; $i++) {
|
||||
my @row = split(/, /,$values[$i]);
|
||||
for ($j = 0; $j <= $#index2; $j++) {
|
||||
$vals[$i][$j] = $row[$j];
|
||||
}
|
||||
}
|
||||
return @vals;
|
||||
}
|
||||
|
||||
sub printMatrix {
|
||||
my $mat = shift;
|
||||
my @matrix = @$mat;
|
||||
my $i; my $j;
|
||||
for ($i=0; $i <= $#index1; $i++) {
|
||||
for ($j = 0; $j <= $#index2; $j++) {
|
||||
print($matrix[$i][$j]." ");
|
||||
}
|
||||
print("\n");
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
@ -45,7 +45,7 @@ def ComputeBranchTargetMissRate(benchmark):
|
||||
'Computes and inserts branch target miss prediction rate.'
|
||||
# *** this is wrong in the verilog test bench
|
||||
(nameString, opt, dataDict) = benchmark
|
||||
branchTargetMissRate = 100.0 * int(dataDict['Br Target Wrong']) / (int(dataDict['Br Count']) + int(dataDict['Jump, JR, ret']) + int(dataDict['ret']))
|
||||
branchTargetMissRate = 100.0 * int(dataDict['Br Target Wrong']) / (int(dataDict['Br Count']) + int(dataDict['Jump, JR, Jal']) + int(dataDict['ret']))
|
||||
dataDict['BTMR'] = branchTargetMissRate
|
||||
|
||||
def ComputeRASMissRate(benchmark):
|
||||
|
||||
206
docs/D-Docker-Install.md
Normal file
206
docs/D-Docker-Install.md
Normal file
@ -0,0 +1,206 @@
|
||||
D Wally Toolchain Docker Container
|
||||
|
||||
Installing RISC-V tools from source gives you maximum control, but has several disadvantages:
|
||||
|
||||
* Building the executables takes several hours.
|
||||
* Linux is poorly standardized, and the build steps might not work on your version
|
||||
* The source files are constantly changing, and the versions you download might not be compatible with this textbook flow.
|
||||
|
||||
Docker is a tools to run applications in a prepackaged container including all of the operating system support required. Wally offers a ~30GB container image with the open-source tools pre-installed from Section D.1. In particular, using the container solves the long build time for gcc and the fussy installation of sail. The container runs on any platform supporting Docker, including Windows and Mac as well as Linux. It can access files outside the container, including local installation of CAD tools such as Questa, and a local clone of the core-v-wally repository.
|
||||
|
||||
Docker can be run on most operating systems, including Linux, Windows, and Mac. The Wally Docker container is hosted at DockerHub (http://docker.io).
|
||||
|
||||
Podman is a more secure and easier-to-use variation of Docker for Linux developed by RedHat. Both Docker and Podman run the same containers.
|
||||
|
||||
D.3.1 Podman Installation on Linux
|
||||
|
||||
A system administrator must install Podman if it is not already present.
|
||||
|
||||
For Ubuntu 20.10 or later:
|
||||
|
||||
$ sudo apt-get -y install podman
|
||||
|
||||
For RedHat / Rocky:
|
||||
|
||||
$ sudo yum -y install podman
|
||||
|
||||
D.3.2 Pulling the Wally Container
|
||||
|
||||
Once Podman is installed, a user can pull the Wally container image. The user must sign up for a free account at docker.io, and will be prompted for the credentials when running podman login.
|
||||
|
||||
$ podman login docker.io
|
||||
$ podman pull docker.io/wallysoc/wally-docker:latest
|
||||
|
||||
D.3.3 Running the Docker Container in Podman
|
||||
|
||||
To activate podman with GUI support, first identify your display port in the /tmp/.X11-unix file as shown below. For example, the user ben is on port X51.
|
||||
|
||||
$ ls -la /tmp/.X11-unix/
|
||||
drwxrwxrwt 2 root root 4096 Jan 6 05:01 .
|
||||
drwxrwxrwt 122 root root 40960 Jan 17 08:09 ..
|
||||
srwxrwxrwx 1 root root 0 Jan 5 08:48 X0
|
||||
srwxrwxrwx 1 xwalter xwalter 0 Jan 5 09:21 X50
|
||||
srwxrwxrwx 1 ben ben 0 Jan 6 05:01 X51
|
||||
|
||||
Then run podman with the display number after the X (51 in this case). The -v options also mount the user’s home directory (/home/ben) and cad tools (/cad) to be visible from the container. Change these as necessary based on your local system configuration.
|
||||
|
||||
$ podman run -it --net=host -e DISPLAY=:51 -v /tmp/.X11-unix:/tmp/.X11-unix -v /home/ben:/home/ben -v /cad:/cad -p 8080:8080 docker.io/wallysoc/wally-docker
|
||||
|
||||
Podman sets up all the RISC-V software in the same location of /opt/riscv as the cad user as discussed previously. This shared directory is called $RISCV. This environmental variable should also be set up within the Docker container automatically and ready to use once the container is run. It is important to understand that Docker containers are self-contained, and any data created within your container is lost when you exit the container. Therefore, be sure to work in your mounted home directory (e.g. /home/ben) to permanently save your work outside the container.
|
||||
|
||||
To have permission to write to your mounted home directory, you must become root inside the Wally container. This is an acceptable practice as the security will be maintained within podman for the user that runs podman. To become root once inside your container:
|
||||
|
||||
$ su # when prompted for password, enter wally
|
||||
|
||||
D.3.4 Cleaning up a Podman Container
|
||||
|
||||
The Docker container image is large, so users may need to clean up a container when they aren’t using it anymore.
|
||||
The images that are loaded can be examined, once you pull the Wally container, by typing:
|
||||
|
||||
$ podman images
|
||||
|
||||
To remove individual podman images, the following Linux command will remove the specific podman image where the image name is obtained from the podman images command (this command also works equally well using the <Image_ID> instead of the <Image_name>, as well).
|
||||
|
||||
$ podman rmi -f <Image_name>
|
||||
|
||||
D.3.5 Running the Docker Container on Windows or MacOS
|
||||
|
||||
Docker Desktop is easiest to use for Mac OS or Windows and can be installed by downloading from http://docker.com. Once the desktop application is installed, users can log into their DockerHub account through the Docker Desktop application and manage their containers easily.
|
||||
|
||||
*** with Questa
|
||||
*** questa unavailable native on Mac
|
||||
|
||||
|
||||
D.3.6 Regenerating the Docker File
|
||||
|
||||
We use the following steps to generate the Docker file. You can adapt them is you wish to make your own custom Docker image, such as one with commercial CAD tools installed in your local environment.
|
||||
|
||||
*** how to use this
|
||||
|
||||
# Compliance Development Environment Image
|
||||
FROM debian
|
||||
|
||||
# UPDATE / UPGRADE
|
||||
RUN apt update
|
||||
|
||||
# INSTALL
|
||||
RUN apt install -y git gawk make texinfo bison flex build-essential python libz-
|
||||
dev libexpat-dev autoconf device-tree-compiler ninja-build libpixman-1-dev build
|
||||
-essential ncurses-base ncurses-bin libncurses5-dev dialog curl wget ftp libgmp-
|
||||
dev python3-pip pkg-config libglib2.0-dev opam build-essential z3 pkg-config zl
|
||||
ib1g-dev verilator cpio bc vim emacs gedit nano
|
||||
|
||||
RUN pip3 install chardet==3.0.4
|
||||
RUN pip3 install urllib3==1.22
|
||||
RUN pip3 install testresources
|
||||
RUN pip3 install riscof --ignore-installed PyYAML
|
||||
RUN echo "root:wally" | chpasswd
|
||||
|
||||
# ADD RISCV
|
||||
WORKDIR /opt/riscv
|
||||
|
||||
# Create a user group 'xyzgroup'
|
||||
ARG USERNAME=cad
|
||||
ARG USER_UID=1000
|
||||
ARG USER_GID=$USER_UID
|
||||
|
||||
# Create the user
|
||||
RUN groupadd --gid $USER_GID $USERNAME \
|
||||
&& useradd --uid $USER_UID --gid $USER_GID -m $USERNAME \
|
||||
# [Optional] Add sudo support. Omit if you don't need to install software af
|
||||
ter connecting.
|
||||
&& apt-get update \
|
||||
&& apt-get install -y sudo \
|
||||
&& echo $USERNAME ALL=\(root\) NOPASSWD:ALL > /etc/sudoers.d/$USERNAME \
|
||||
&& chmod 0440 /etc/sudoers.d/$USERNAME
|
||||
|
||||
# Change RISCV user
|
||||
run chown -Rf cad:cad /opt
|
||||
|
||||
# Add cad user
|
||||
USER $USERNAME
|
||||
|
||||
# SET ENVIRONMENT VARIABLES
|
||||
ENV RISCV=/opt/riscv
|
||||
ENV PATH=$PATH:$RISCV/bin
|
||||
|
||||
# TOOLCHAIN
|
||||
RUN git clone https://github.com/riscv/riscv-gnu-toolchain && \
|
||||
cd riscv-gnu-toolchain && \
|
||||
./configure --prefix=${RISCV} --enable-multilib --with-multilib-generator="r
|
||||
v32e-ilp32e--;rv32i-ilp32--;rv32im-ilp32--;rv32iac-ilp32--;rv32imac-ilp32--;rv32
|
||||
imafc-ilp32f--;rv32imafdc-ilp32d--;rv64i-lp64--;rv64ic-lp64--;rv64iac-lp64--;rv6
|
||||
4imac-lp64--;rv64imafdc-lp64d--;rv64im-lp64--;" && \
|
||||
make --jobs && \
|
||||
make install
|
||||
|
||||
# elf2hex
|
||||
ENV PATH=$RISCV/riscv-gnu-toolchain/bin:$PATH
|
||||
WORKDIR /opt/riscv
|
||||
RUN git clone https://github.com/sifive/elf2hex.git && \
|
||||
cd elf2hex && \
|
||||
autoreconf -i && \
|
||||
./configure --target=riscv64-unknown-elf --prefix=$RISCV && \
|
||||
make && \
|
||||
make install
|
||||
|
||||
# QEMU
|
||||
WORKDIR /opt/riscv
|
||||
RUN git clone --recurse-submodules https://github.com/qemu/qemu && \
|
||||
cd qemu && \
|
||||
./configure --target-list=riscv64-softmmu --prefix=$RISCV && \
|
||||
make --jobs && \
|
||||
make install
|
||||
|
||||
# Spike
|
||||
WORKDIR /opt/riscv
|
||||
RUN git clone https://github.com/riscv-software-src/riscv-isa-sim && \
|
||||
mkdir riscv-isa-sim/build && \
|
||||
cd riscv-isa-sim/build && \
|
||||
../configure --prefix=$RISCV --enable-commitlog && \
|
||||
make --jobs && \
|
||||
make install && \
|
||||
cd ../arch_test_target/spike/device && \
|
||||
sed -i 's/--isa=rv32ic/--isa=rv32iac/' rv32i_m/privilege/Makefile.include && \
|
||||
sed -i 's/--isa=rv64ic/--isa=rv64iac/' rv64i_m/privilege/Makefile.include
|
||||
|
||||
# SAIL
|
||||
WORKDIR /opt/riscv
|
||||
RUN opam init -y --disable-sandboxing
|
||||
RUN opam switch create ocaml-base-compiler.4.06.1
|
||||
RUN opam install sail -y
|
||||
RUN eval $(opam config env) && \
|
||||
cd $RISCV && \
|
||||
git clone https://github.com/riscv/sail-riscv.git && \
|
||||
cd sail-riscv && \
|
||||
make && \
|
||||
ARCH=RV32 make && \
|
||||
ARCH=RV64 make && \
|
||||
ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV64 $RISCV/bin/riscv_sim_RV64 &&
|
||||
\
|
||||
ln -s $RISCV/sail-riscv/c_emulator/riscv_sim_RV32 $RISCV/bin/riscv_sim_RV32
|
||||
|
||||
# Buildroot
|
||||
WORKDIR /opt/riscv
|
||||
RUN git clone --recurse-submodules https://stineje:ghp_kXIHqiMSv4tFec2BCAvrhSrIh
|
||||
3KNUD06IejU@github.com/davidharrishmc/riscv-wally.git
|
||||
ENV export WALLY=/opt/riscv/riscv-wally
|
||||
RUN git clone https://github.com/buildroot/buildroot.git && \
|
||||
cd buildroot && \
|
||||
git checkout 2021.05 && \
|
||||
cp -r /opt/riscv/riscv-wally/linux/buildroot-config-src/wally ./board && \
|
||||
cp ./board/wally/main.config .config && \
|
||||
make --jobs
|
||||
|
||||
# change to cad's hometown
|
||||
WORKDIR /home/cad
|
||||
|
||||
|
||||
D.3.7 Integrating Commercial CAD Tools into a Local Docker Container
|
||||
|
||||
|
||||
|
||||
RISC-V System-on-Chip Design Lecture Notes
|
||||
© 2023 D. Harris, J. Stine, , R. Thompson, and S. Harris
|
||||
These notes may be used and modified for educational and/or non-commercial purposes so long as the source is attributed.
|
||||
|
||||
@ -1,3 +1,28 @@
|
||||
###########################################
|
||||
## Dockerfile
|
||||
##
|
||||
## Written: james.stine@okstate.edu 28 January 2023
|
||||
## Modified:
|
||||
##
|
||||
## Purpose: Dockerfile for Wally docker container creation
|
||||
##
|
||||
## A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
##
|
||||
## Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
##
|
||||
## SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
##
|
||||
## Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
## except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
## may obtain a copy of the License at
|
||||
##
|
||||
## https:##solderpad.org#licenses#SHL-2.1#
|
||||
##
|
||||
## Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
## License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
## either express or implied. See the License for the specific language governing permissions
|
||||
## and limitations under the License.
|
||||
################################################################################################
|
||||
# Compliance Development Environment Image
|
||||
FROM debian
|
||||
|
||||
@ -4,7 +4,7 @@ $(TARGET).objdump: $(TARGET)
|
||||
riscv64-unknown-elf-objdump -S -D $(TARGET) > $(TARGET).objdump
|
||||
|
||||
$(TARGET): $(TARGET).c Makefile
|
||||
riscv64-unknown-elf-gcc -o $(TARGET) -g -O\
|
||||
riscv64-unknown-elf-gcc -o $(TARGET) -gdwarf-2 -O\
|
||||
-march=rv64gc -mabi=lp64d -mcmodel=medany \
|
||||
-nostdlib -static -lm -fno-tree-loop-distribute-patterns \
|
||||
-T../common/test.ld -I../common \
|
||||
|
||||
@ -48,3 +48,6 @@ Create pull request
|
||||
1. git pull upstream main # fetch and merge the upstream openhwgroup/cvw into your local clone
|
||||
3. git push # sync your fork with the upstream and clone
|
||||
|
||||
|
||||
If the pull request need changes, modify accordingly, commit, and push changes back to the fork.
|
||||
The pull request will automatically update.
|
||||
|
||||
@ -11,18 +11,19 @@
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
@ -41,12 +42,11 @@
|
||||
`define ZICOUNTERS_SUPPORTED 1
|
||||
`define ZFH_SUPPORTED 0
|
||||
`define COUNTERS 32
|
||||
`define DESIGN_COMPILER 0
|
||||
|
||||
// LSU microarchitectural Features
|
||||
`define BUS 1
|
||||
`define DCACHE 1
|
||||
`define ICACHE 1
|
||||
`define BUS_SUPPORTED 1
|
||||
`define DCACHE_SUPPORTED 1
|
||||
`define ICACHE_SUPPORTED 1
|
||||
`define VIRTMEM_SUPPORTED 1
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
`define BIGENDIAN_SUPPORTED 1
|
||||
@ -126,9 +126,10 @@
|
||||
// Interrupt configuration
|
||||
`define PLIC_NUM_SRC 53
|
||||
`define PLIC_UART_ID 10
|
||||
`define PLIC_GPIO_ID 3
|
||||
|
||||
`define BPRED_ENABLED 1
|
||||
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define BPRED_SUPPORTED 1
|
||||
`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define TESTSBP 0
|
||||
`define BPRED_SIZE 10
|
||||
|
||||
|
||||
@ -11,25 +11,25 @@
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
|
||||
`define FPGA 1
|
||||
`define QEMU 0
|
||||
`define DESIGN_COMPILER 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 64
|
||||
@ -43,12 +43,11 @@
|
||||
`define ZICOUNTERS_SUPPORTED 1
|
||||
`define ZFH_SUPPORTED 0
|
||||
`define COUNTERS 32
|
||||
`define DESIGN_COMPILER 0
|
||||
|
||||
// LSU microarchitectural Features
|
||||
`define BUS 1
|
||||
`define DCACHE 1
|
||||
`define ICACHE 1
|
||||
`define BUS_SUPPORTED 1
|
||||
`define DCACHE_SUPPORTED 1
|
||||
`define ICACHE_SUPPORTED 1
|
||||
`define VIRTMEM_SUPPORTED 1
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
`define BIGENDIAN_SUPPORTED 1
|
||||
@ -72,7 +71,7 @@
|
||||
`define IDIV_ON_FPU 1
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 64
|
||||
`define PMP_ENTRIES 16
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 64'h0000000000001000
|
||||
@ -136,11 +135,10 @@
|
||||
// Interrupt configuration
|
||||
`define PLIC_NUM_SRC 53
|
||||
`define PLIC_UART_ID 10
|
||||
`define PLIC_GPIO_ID 3
|
||||
|
||||
`define TWO_BIT_PRELOAD "../config/fpga/twoBitPredictor.txt"
|
||||
`define BTB_PRELOAD "../config/fpga/BTBPredictor.txt"
|
||||
`define BPRED_ENABLED 1
|
||||
`define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
|
||||
`define BPRED_SUPPORTED 1
|
||||
`define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
|
||||
`define TESTSBP 1
|
||||
`define BPRED_SIZE 10
|
||||
|
||||
|
||||
@ -11,25 +11,25 @@
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
|
||||
`define FPGA 0
|
||||
`define QEMU 0
|
||||
`define DESIGN_COMPILER 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 32
|
||||
@ -46,9 +46,9 @@
|
||||
`define ZFH_SUPPORTED 0
|
||||
|
||||
// LSU microarchitectural Features
|
||||
`define BUS 1
|
||||
`define DCACHE 0
|
||||
`define ICACHE 0
|
||||
`define BUS_SUPPORTED 1
|
||||
`define DCACHE_SUPPORTED 0
|
||||
`define ICACHE_SUPPORTED 0
|
||||
`define VIRTMEM_SUPPORTED 0
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 0
|
||||
`define BIGENDIAN_SUPPORTED 0
|
||||
@ -69,7 +69,7 @@
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define IDIV_BITSPERCYCLE 1
|
||||
`define IDIV_ON_FPU 1
|
||||
`define IDIV_ON_FPU 0
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 0
|
||||
@ -132,8 +132,8 @@
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define BPRED_ENABLED 0
|
||||
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define BPRED_SUPPORTED 0
|
||||
`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define TESTSBP 0
|
||||
`define BPRED_SIZE 10
|
||||
|
||||
|
||||
@ -11,25 +11,25 @@
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
|
||||
`define FPGA 0
|
||||
`define QEMU 0
|
||||
`define DESIGN_COMPILER 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 32
|
||||
@ -45,9 +45,9 @@
|
||||
`define ZFH_SUPPORTED 0
|
||||
|
||||
// LSU microarchitectural Features
|
||||
`define BUS 1
|
||||
`define DCACHE 1
|
||||
`define ICACHE 1
|
||||
`define BUS_SUPPORTED 1
|
||||
`define DCACHE_SUPPORTED 1
|
||||
`define ICACHE_SUPPORTED 1
|
||||
`define VIRTMEM_SUPPORTED 1
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
`define BIGENDIAN_SUPPORTED 1
|
||||
@ -68,7 +68,7 @@
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define IDIV_BITSPERCYCLE 4
|
||||
`define IDIV_ON_FPU 1
|
||||
`define IDIV_ON_FPU 0
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 16
|
||||
@ -131,8 +131,8 @@
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define BPRED_ENABLED 1
|
||||
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define BPRED_SUPPORTED 1
|
||||
`define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define TESTSBP 0
|
||||
`define BPRED_SIZE 10
|
||||
|
||||
|
||||
@ -11,25 +11,25 @@
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
|
||||
`define FPGA 0
|
||||
`define QEMU 0
|
||||
`define DESIGN_COMPILER 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 32
|
||||
@ -46,9 +46,9 @@
|
||||
`define ZFH_SUPPORTED 0
|
||||
|
||||
// LSU microarchitectural Features
|
||||
`define BUS 0
|
||||
`define DCACHE 0
|
||||
`define ICACHE 0
|
||||
`define BUS_SUPPORTED 0
|
||||
`define DCACHE_SUPPORTED 0
|
||||
`define ICACHE_SUPPORTED 0
|
||||
`define VIRTMEM_SUPPORTED 0
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
`define BIGENDIAN_SUPPORTED 0
|
||||
@ -69,10 +69,10 @@
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define IDIV_BITSPERCYCLE 4
|
||||
`define IDIV_ON_FPU 1
|
||||
`define IDIV_ON_FPU 0
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 64
|
||||
`define PMP_ENTRIES 0
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 32'h80000000
|
||||
@ -132,8 +132,8 @@
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define BPRED_ENABLED 1
|
||||
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define BPRED_SUPPORTED 0
|
||||
`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define TESTSBP 0
|
||||
`define BPRED_SIZE 10
|
||||
|
||||
|
||||
@ -11,25 +11,25 @@
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
|
||||
`define FPGA 0
|
||||
`define QEMU 0
|
||||
`define DESIGN_COMPILER 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 32
|
||||
@ -45,9 +45,9 @@
|
||||
`define ZFH_SUPPORTED 0
|
||||
|
||||
// LSU microarchitectural Features
|
||||
`define BUS 1
|
||||
`define DCACHE 0
|
||||
`define ICACHE 0
|
||||
`define BUS_SUPPORTED 1
|
||||
`define DCACHE_SUPPORTED 0
|
||||
`define ICACHE_SUPPORTED 0
|
||||
`define VIRTMEM_SUPPORTED 0
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
`define BIGENDIAN_SUPPORTED 0
|
||||
@ -68,7 +68,7 @@
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define IDIV_BITSPERCYCLE 4
|
||||
`define IDIV_ON_FPU 1
|
||||
`define IDIV_ON_FPU 0
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 0
|
||||
@ -131,8 +131,8 @@
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define BPRED_ENABLED 1
|
||||
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define BPRED_SUPPORTED 0
|
||||
`define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define TESTSBP 0
|
||||
`define BPRED_SIZE 10
|
||||
|
||||
|
||||
@ -11,25 +11,25 @@
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
|
||||
`define FPGA 0
|
||||
`define QEMU 0
|
||||
`define DESIGN_COMPILER 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 64
|
||||
@ -46,9 +46,9 @@
|
||||
`define ZFH_SUPPORTED 1
|
||||
|
||||
// LSU microarchitectural Features
|
||||
`define BUS 1
|
||||
`define DCACHE 1
|
||||
`define ICACHE 1
|
||||
`define BUS_SUPPORTED 1
|
||||
`define DCACHE_SUPPORTED 1
|
||||
`define ICACHE_SUPPORTED 1
|
||||
`define VIRTMEM_SUPPORTED 1
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
`define BIGENDIAN_SUPPORTED 1
|
||||
@ -72,7 +72,7 @@
|
||||
`define IDIV_ON_FPU 1
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 64
|
||||
`define PMP_ENTRIES 16
|
||||
|
||||
// Address space
|
||||
`define RESET_VECTOR 64'h0000000080000000
|
||||
@ -134,8 +134,8 @@
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define BPRED_ENABLED 1
|
||||
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define BPRED_SUPPORTED 1
|
||||
`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define TESTSBP 0
|
||||
`define BPRED_SIZE 10
|
||||
|
||||
|
||||
@ -11,25 +11,25 @@
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
|
||||
`define FPGA 0
|
||||
`define QEMU 0
|
||||
`define DESIGN_COMPILER 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 64
|
||||
@ -46,9 +46,9 @@
|
||||
`define ZFH_SUPPORTED 0
|
||||
|
||||
// LSU microarchitectural Features
|
||||
`define BUS 1
|
||||
`define DCACHE 1
|
||||
`define ICACHE 1
|
||||
`define BUS_SUPPORTED 1
|
||||
`define DCACHE_SUPPORTED 1
|
||||
`define ICACHE_SUPPORTED 1
|
||||
`define VIRTMEM_SUPPORTED 1
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
`define BIGENDIAN_SUPPORTED 1
|
||||
@ -134,10 +134,8 @@
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define BPRED_ENABLED 1
|
||||
//`define BPTYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
|
||||
`define BPTYPE "BPSPECULATIVEGLOBAL" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
|
||||
//`define BPTYPE "BPFOLDEDGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
|
||||
`define BPRED_SUPPORTED 1
|
||||
`define BPRED_TYPE "BPSPECULATIVEGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE or BPSPECULATIVEGLOBAL or BPSPECULATIVEGSHARE or BPOLDGSHARE or BPOLDGSHARE2
|
||||
`define TESTSBP 0
|
||||
`define BPRED_SIZE 10
|
||||
|
||||
|
||||
@ -11,25 +11,25 @@
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// include shared configuration
|
||||
`include "wally-shared.vh"
|
||||
|
||||
`define FPGA 0
|
||||
`define QEMU 0
|
||||
`define DESIGN_COMPILER 0
|
||||
|
||||
// RV32 or RV64: XLEN = 32 or 64
|
||||
`define XLEN 64
|
||||
@ -46,9 +46,9 @@
|
||||
`define ZFH_SUPPORTED 0
|
||||
|
||||
// LSU microarchitectural Features
|
||||
`define BUS 0
|
||||
`define DCACHE 0
|
||||
`define ICACHE 0
|
||||
`define BUS_SUPPORTED 0
|
||||
`define DCACHE_SUPPORTED 0
|
||||
`define ICACHE_SUPPORTED 0
|
||||
`define VIRTMEM_SUPPORTED 0
|
||||
`define VECTORED_INTERRUPTS_SUPPORTED 1
|
||||
`define BIGENDIAN_SUPPORTED 0
|
||||
@ -69,7 +69,7 @@
|
||||
// Integer Divider Configuration
|
||||
// IDIV_BITSPERCYCLE must be 1, 2, or 4
|
||||
`define IDIV_BITSPERCYCLE 4
|
||||
`define IDIV_ON_FPU 1
|
||||
`define IDIV_ON_FPU 0
|
||||
|
||||
// Legal number of PMP entries are 0, 16, or 64
|
||||
`define PMP_ENTRIES 0
|
||||
@ -134,8 +134,8 @@
|
||||
`define PLIC_GPIO_ID 3
|
||||
`define PLIC_UART_ID 10
|
||||
|
||||
`define BPRED_ENABLED 0
|
||||
`define BPTYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define BPRED_SUPPORTED 0
|
||||
`define BPRED_TYPE "BPGSHARE" // BPLOCALPAg or BPGLOBAL or BPTWOBIT or BPGSHARE
|
||||
`define TESTSBP 0
|
||||
`define BPRED_SIZE 10
|
||||
|
||||
|
||||
@ -15,18 +15,19 @@
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// constants defining different privilege modes
|
||||
// defined in Table 1.1 of the privileged spec
|
||||
|
||||
@ -9,18 +9,19 @@
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation
|
||||
// files (the "Software"), to deal in the Software without restriction, including without limitation the rights to use, copy,
|
||||
// modify, merge, publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the Software
|
||||
// is furnished to do so, subject to the following conditions:
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software.
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
|
||||
// OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT
|
||||
// OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
///////////////////////////////////////////
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// division constants
|
||||
`define RADIX 32'h4
|
||||
|
||||
@ -204,9 +204,6 @@ def main():
|
||||
# Count the number of failures
|
||||
if num_fail:
|
||||
print(f"{bcolors.FAIL}Regression failed with %s failed configurations{bcolors.ENDC}" % num_fail)
|
||||
# Remind the user to try `make allclean`, since it may be needed if test
|
||||
# cases have changed
|
||||
print("Reminder: have you run `make allclean`?")
|
||||
else:
|
||||
print(f"{bcolors.OKGREEN}SUCCESS! All tests ran without failures{bcolors.ENDC}")
|
||||
return num_fail
|
||||
|
||||
@ -1,4 +1,5 @@
|
||||
onerror {resume}
|
||||
quietly virtual signal -install /testbench/dut/core/ifu/bpred/bpred { /testbench/dut/core/ifu/bpred/bpred/PostSpillInstrRawF[11:7]} rd
|
||||
quietly WaveActivateNextPane {} 0
|
||||
add wave -noupdate /testbench/clk
|
||||
add wave -noupdate /testbench/reset
|
||||
@ -36,17 +37,16 @@ add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/
|
||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallE
|
||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallM
|
||||
add wave -noupdate -group HDU -expand -group Stall -color Orange /testbench/dut/core/StallW
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/InstrFName
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrE
|
||||
add wave -noupdate -group {instruction pipeline} /testbench/dut/core/ifu/InstrM
|
||||
add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCNextF
|
||||
add wave -noupdate -expand -group PCS /testbench/dut/core/PCF
|
||||
add wave -noupdate -expand -group PCS /testbench/dut/core/ifu/PCD
|
||||
add wave -noupdate -expand -group PCS /testbench/dut/core/PCE
|
||||
add wave -noupdate -expand -group PCS /testbench/dut/core/PCM
|
||||
add wave -noupdate -expand -group PCS /testbench/PCW
|
||||
add wave -noupdate -expand -group {instruction pipeline} /testbench/InstrFName
|
||||
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/PostSpillInstrRawF
|
||||
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrD
|
||||
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrE
|
||||
add wave -noupdate -expand -group {instruction pipeline} /testbench/dut/core/ifu/InstrM
|
||||
add wave -noupdate -group PCS /testbench/dut/core/ifu/PCNextF
|
||||
add wave -noupdate -group PCS /testbench/dut/core/ifu/PCD
|
||||
add wave -noupdate -group PCS /testbench/dut/core/PCE
|
||||
add wave -noupdate -group PCS /testbench/dut/core/PCM
|
||||
add wave -noupdate -group PCS /testbench/PCW
|
||||
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/PCD
|
||||
add wave -noupdate -group {Decode Stage} /testbench/dut/core/ifu/InstrD
|
||||
add wave -noupdate -group {Decode Stage} /testbench/InstrDName
|
||||
@ -85,29 +85,20 @@ add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SEPC_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/SSTATUS_REGW
|
||||
add wave -noupdate -group CSRs /testbench/dut/core/priv/priv/csr/STVEC_REGW
|
||||
add wave -noupdate -group Bpred -group {branch update selection inputs} -divider {class check}
|
||||
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBValidF
|
||||
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BPInstrClassF
|
||||
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/BTBPredPCF
|
||||
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
|
||||
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/LookUpPCIndex
|
||||
add wave -noupdate -group Bpred -expand -group prediction /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/TargetPC
|
||||
add wave -noupdate -group Bpred -expand -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
|
||||
add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePCIndex
|
||||
add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget
|
||||
add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateEN
|
||||
add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdatePC
|
||||
add wave -noupdate -group Bpred -expand -group update -expand -group BTB /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/UpdateTarget
|
||||
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/TargetWrongE
|
||||
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE
|
||||
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE
|
||||
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/InstrClassE
|
||||
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE
|
||||
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE
|
||||
add wave -noupdate -group Bpred -expand -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
|
||||
add wave -noupdate -group Bpred -group prediction /testbench/dut/core/ifu/bpred/bpred/RASPCF
|
||||
add wave -noupdate -group Bpred -group prediction -expand -group ex /testbench/dut/core/ifu/bpred/bpred/PCSrcE
|
||||
add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/TargetWrongE
|
||||
add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE
|
||||
add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE
|
||||
add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/InstrClassE
|
||||
add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE
|
||||
add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredClassNonCFIWrongE
|
||||
add wave -noupdate -group Bpred -group {bp wrong} /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
|
||||
add wave -noupdate -group Bpred /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNextF
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCF
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCPlus2or4F
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/bpred/bpred/PCNext0F
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/PCNext1F
|
||||
add wave -noupdate -group {PCNext Generation} /testbench/dut/core/ifu/BPPredWrongE
|
||||
add wave -noupdate -group RegFile -expand /testbench/dut/core/ieu/dp/regf/rf
|
||||
@ -148,20 +139,15 @@ add wave -noupdate -group Forward /testbench/dut/core/ieu/fw/RdW
|
||||
add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/ALUResultE
|
||||
add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcAE
|
||||
add wave -noupdate -group {alu execution stage} /testbench/dut/core/ieu/dp/SrcBE
|
||||
add wave -noupdate -group AHB -expand -group multicontroller -color Gold /testbench/dut/core/ebu/ebu/CurrState
|
||||
add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUReq
|
||||
add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUReq
|
||||
add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/both
|
||||
add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUSave
|
||||
add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFURestore
|
||||
add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUDisable
|
||||
add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUDisable
|
||||
add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/IFUSelect
|
||||
add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/LSUSelect
|
||||
add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/BeatCount
|
||||
add wave -noupdate -group AHB -expand -group multicontroller /testbench/dut/core/ebu/ebu/FinalBeat
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/Threshold
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST
|
||||
add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHTRANS
|
||||
add wave -noupdate -group AHB -expand -group IFU /testbench/dut/core/ebu/ebu/IFUHADDR
|
||||
@ -190,199 +176,204 @@ add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HBURST
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HPROT
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HTRANS
|
||||
add wave -noupdate -group AHB /testbench/dut/core/ebu/ebu/HMASTLOCK
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/SelHPTW
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/LSUStallM
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/ReadDataM
|
||||
add wave -noupdate -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/FWriteDataM
|
||||
add wave -noupdate -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/ebu/ebu/HCLK
|
||||
add wave -noupdate -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/BusStall
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/LSUHWDATA
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW
|
||||
add wave -noupdate -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW
|
||||
add wave -noupdate -group lsu -expand -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrE
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/IEUAdrM
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
|
||||
add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CAdr
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded
|
||||
add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
||||
add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr
|
||||
add wave -noupdate -group lsu -expand -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
|
||||
add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag
|
||||
add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn
|
||||
add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn
|
||||
add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag
|
||||
add wave -noupdate -group lsu -expand -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM[62]}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/we}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
|
||||
add wave -noupdate -group lsu -expand -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData
|
||||
add wave -noupdate -group lsu -expand -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
add wave -noupdate -group lsu -expand -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
|
||||
add wave -noupdate -group lsu -expand -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord
|
||||
add wave -noupdate -group lsu -expand -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
|
||||
add wave -noupdate -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
|
||||
add wave -noupdate -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
|
||||
add wave -noupdate -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWalk
|
||||
add wave -noupdate -group lsu -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/WalkerState
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PCF
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWAdr
|
||||
add wave -noupdate -group lsu -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PTE
|
||||
add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF
|
||||
add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM
|
||||
add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ITLBWriteF
|
||||
add wave -noupdate -group lsu -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWriteM
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/SelHPTW
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/LSUStallM
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataWordMuxM
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/ReadDataM
|
||||
add wave -noupdate -expand -group lsu -radix hexadecimal /testbench/dut/core/lsu/WriteDataM
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/FWriteDataM
|
||||
add wave -noupdate -expand -group lsu /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
|
||||
add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/ebu/ebu/HCLK
|
||||
add wave -noupdate -expand -group lsu -group bus -color Gold /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/CurrState
|
||||
add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/AHBBuscachefsm/HREADY
|
||||
add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/BusStall
|
||||
add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HTRANS
|
||||
add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/FetchBuffer
|
||||
add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/HRDATA
|
||||
add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/LSUHWDATA
|
||||
add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/BusStall
|
||||
add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusRW
|
||||
add wave -noupdate -expand -group lsu -group bus /testbench/dut/core/lsu/bus/dcache/ahbcacheinterface/CacheBusAck
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CacheRW
|
||||
add wave -noupdate -expand -group lsu -group dcache -color Gold /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/CurrState
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetValid
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SetDirty
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrE
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/IEUAdrM
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ClearDirtyWay}
|
||||
add wave -noupdate -expand -group lsu -group dcache {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -color {Orange Red} {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/VictimWay
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -expand -group DETAILS -expand /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/Intermediate
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUUpdate
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {replacement policy} -expand -group DETAILS /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/WayExpanded
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/LineDirty
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/NextFlushAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush -radix hexadecimal /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushWayFlag
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushWayCntEn
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/FlushAdrCntEn
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/FlushAdrFlag
|
||||
add wave -noupdate -expand -group lsu -group dcache -group flush /testbench/dut/core/lsu/bus/dcache/dcache/cachefsm/SelFlush
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/VictimWay
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/SelAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/PAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/NextLRU
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/CurrLRU
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUWriteEn
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataLine
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/WordOffsetAddr
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/HitWay
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/ValidWay
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group Victim {/testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory[0]}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group Victim /testbench/dut/core/lsu/bus/dcache/dcache/vict/cacheLRU/LRUMemory
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SelectedWriteWordEn}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetValidWay}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/SetDirtyWay}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/CacheTagMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[0]/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[1]/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM[62]}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way0 -group Way0Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SelectedWriteWordEn}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetValidWay}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/SetDirtyWay}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/CacheTagMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[0]/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[1]/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way1 -group Way1Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SelectedWriteWordEn}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetValidWay}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/SetDirtyWay}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/CacheTagMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[0]/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[1]/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way2 -group Way2Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SelectedWriteWordEn}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetValidWay}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/SetDirtyWay}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -label TAG {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/CacheTagMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/DirtyBits}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[0]/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[1]/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word2 -expand {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/we}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -expand -group way3 -group Way3Word3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearValid
|
||||
add wave -noupdate -expand -group lsu -group dcache -expand -group {Cache SRAM writes} -group valid/dirty /testbench/dut/core/lsu/bus/dcache/dcache/ClearDirty
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/CAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/HitWay}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ValidWay}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way0 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[0]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/HitWay}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ValidWay}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -expand -group way1 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[1]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/HitWay}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ValidWay}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way2 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[2]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/HitWay}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ValidWay}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/Dirty}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} -group way3 {/testbench/dut/core/lsu/bus/dcache/dcache/CacheWays[3]/ReadTag}
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Cache SRAM read} /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/NextAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/PAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/FlushCache
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheStall
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/ReadDataWordM
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {CPU side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheWriteData
|
||||
add wave -noupdate -expand -group lsu -group dcache -group status /testbench/dut/core/lsu/bus/dcache/dcache/HitWay
|
||||
add wave -noupdate -expand -group lsu -group dcache -group status -color {Medium Orchid} /testbench/dut/core/lsu/bus/dcache/dcache/CacheHit
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAdr
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/CacheBusAck
|
||||
add wave -noupdate -expand -group lsu -group dcache -group {Memory Side} /testbench/dut/core/lsu/bus/dcache/dcache/ReadDataWord
|
||||
add wave -noupdate -expand -group lsu -group dcache /testbench/dut/core/lsu/bus/dcache/dcache/FlushWay
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/VAdr
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/EffectivePrivilegeMode
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/HitPageType
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/Translate
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/tlbcontrol/DisableTranslation
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBMiss
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/TLBHit
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/PhysicalAddress
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/TLBPageFault
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/LoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group faults /testbench/dut/core/lsu/dmmu/dmmu/StoreAmoAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group dtlb /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBPAdr
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PTE
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/PageTypeWriteVal
|
||||
add wave -noupdate -expand -group lsu -group dtlb -expand -group write /testbench/dut/core/lsu/dmmu/dmmu/tlb/tlb/TLBWrite
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PhysicalAddress
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/SelRegions
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Cacheable
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/Idempotent
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/pmachecker/PMAAccessFault
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAInstrAccessFaultF
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMALoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group pma /testbench/dut/core/lsu/dmmu/dmmu/PMAStoreAmoAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PhysicalAddress
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/ReadAccessM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/WriteAccessM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPADDR_ARRAY_REGW
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/pmpchecker/PMPCFG_ARRAY_REGW
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPInstrAccessFaultF
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPLoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -group pmp /testbench/dut/core/lsu/dmmu/dmmu/PMPStoreAmoAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWalk
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -color Gold /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/WalkerState
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWAdr
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PTE
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/PCFSpill
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/ITLBMissF
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/DTLBMissM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/ITLBWriteF
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group types /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/DTLBWriteM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSULoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LSUStoreAmoAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/HPTWInstrAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/LoadAccessFaultM
|
||||
add wave -noupdate -expand -group lsu -expand -group ptwalker -expand -group faults /testbench/dut/core/lsu/VIRTMEM_SUPPORTED/hptw/StoreAmoAccessFaultM
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/UARTIntr
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/GPIOIntr
|
||||
add wave -noupdate -group plic /testbench/dut/uncore/uncore/plic/plic/MExtInt
|
||||
@ -463,82 +454,78 @@ add wave -noupdate -group {debug trace} -expand -group mem /testbench/dut/core/P
|
||||
add wave -noupdate -group {debug trace} -expand -group mem -color Brown /testbench/dut/core/hzu/TrapM
|
||||
add wave -noupdate -group {debug trace} -expand -group wb /testbench/PCW
|
||||
add wave -noupdate -group {pc selection} /testbench/dut/core/ifu/PCNext2F
|
||||
add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillF
|
||||
add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/CurrState
|
||||
add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SpillDataLine0
|
||||
add wave -noupdate -group ifu -expand -group spill /testbench/dut/core/ifu/SpillSupport/spillsupport/SelSpillF
|
||||
add wave -noupdate -group ifu /testbench/dut/core/ifu/InstrRawF
|
||||
add wave -noupdate -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF
|
||||
add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE
|
||||
add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST
|
||||
add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS
|
||||
add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE
|
||||
add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR
|
||||
add wave -noupdate -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush
|
||||
add wave -noupdate -group ifu -expand -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState
|
||||
add wave -noupdate -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState
|
||||
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF
|
||||
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr
|
||||
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCNextF
|
||||
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF
|
||||
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/cachefsm/AnyMiss
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/FinalInstrRawF
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr
|
||||
add wave -noupdate -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck
|
||||
add wave -noupdate -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/bwe}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/bwe}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/bwe}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/bwe}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/bwe}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/bwe}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/bwe}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/bwe}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/bwe}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/bwe}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/bwe}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/bwe}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/bwe}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/bwe}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/bwe}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/bwe}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/dout}
|
||||
add wave -noupdate -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
|
||||
add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/ITLBMissF
|
||||
add wave -noupdate -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
|
||||
add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/InstrRawF
|
||||
add wave -noupdate -expand -group ifu /testbench/dut/core/ifu/PostSpillInstrRawF
|
||||
add wave -noupdate -expand -group ifu -expand -group Spill /testbench/dut/core/ifu/Spill/spill/CurrState
|
||||
add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HSIZE
|
||||
add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HBURST
|
||||
add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HTRANS
|
||||
add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HWRITE
|
||||
add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/HADDR
|
||||
add wave -noupdate -expand -group ifu -expand -group bus /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/Flush
|
||||
add wave -noupdate -expand -group ifu -expand -group bus -color Gold /testbench/dut/core/ifu/bus/icache/ahbcacheinterface/AHBBuscachefsm/CurrState
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -color Gold /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CurrState
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/ITLBMissF
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/SelAdr
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/PCNextF
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/PCPF
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/cachefsm/AnyMiss
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/bus/icache/icache/HitWay
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group {fsm out and control} /testbench/dut/core/ifu/ICacheStallF
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/CacheBusAdr
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -expand -group memory /testbench/dut/core/ifu/bus/icache/icache/cachefsm/CacheBusAck
|
||||
add wave -noupdate -expand -group ifu -expand -group icache /testbench/dut/core/ifu/bus/icache/icache/VictimWay
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/bwe}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/dout}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/bwe}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/dout}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/bwe}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/dout}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/bwe}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/dout}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way3 -group way3word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[3]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/bwe}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/dout}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/bwe}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/dout}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/bwe}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/dout}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/bwe}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/dout}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way2 -group way2word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[2]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/bwe}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/dout}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/bwe}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/dout}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/bwe}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/dout}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/bwe}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/dout}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way1 -group way1word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[1]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/bwe}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/dout}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word0 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[0]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/bwe}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/dout}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way0 -expand -group way0word1 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[1]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/bwe}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/dout}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word2 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[2]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/bwe}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/dout}
|
||||
add wave -noupdate -expand -group ifu -expand -group icache -group way0 -group way0word3 {/testbench/dut/core/ifu/bus/icache/icache/CacheWays[0]/word[3]/CacheDataMem/RAM}
|
||||
add wave -noupdate -expand -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/TLBWrite
|
||||
add wave -noupdate -expand -group ifu -expand -group itlb /testbench/dut/core/ifu/ITLBMissF
|
||||
add wave -noupdate -expand -group ifu -expand -group itlb /testbench/dut/core/ifu/immu/immu/PhysicalAddress
|
||||
add wave -noupdate -expand -group {Performance Counters} -label MCYCLE -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[0]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -label MINSTRET -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[2]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -label {LOAD STORE HAZARD} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[3]}
|
||||
@ -549,6 +536,7 @@ add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -lab
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {RAS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[8]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {RETURN INSTRUCTION} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[9]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {BP CLASS WRONG} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[10]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group BRP -label {Branch Predictor Wrong} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[15]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group ICACHE -label {ICACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[13]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group ICACHE -label {ICACHE MISS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[14]}
|
||||
add wave -noupdate -expand -group {Performance Counters} -expand -group DCACHE -label {DCACHE ACCESS} -radix unsigned {/testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW[11]}
|
||||
@ -571,7 +559,6 @@ add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/FRD3E
|
||||
add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcAE
|
||||
add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/ForwardedSrcBE
|
||||
add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/Funct3E
|
||||
add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/MDUE
|
||||
add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/W64E
|
||||
add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/X
|
||||
add wave -noupdate -group FPU /testbench/dut/core/fpu/fpu/unpack/Y
|
||||
@ -584,27 +571,66 @@ add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELRegions
|
||||
add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELNoneD
|
||||
add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HSELPLICD
|
||||
add wave -noupdate -group uncore /testbench/dut/uncore/uncore/HRDATA
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchNextX
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchD
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchE
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchM
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchW
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextD
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/OldGHRE
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRW
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrW
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrM
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionW
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PtrQ
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PopF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/PushE
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/RASPCF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/RASPredictor/RepairD
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredictionInstrClassWrongE
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassE
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassE
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/rd
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PostSpillInstrRawF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BTBPredPCWrongM
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredictionPCWrongE
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetWrongE
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/FallThroughWrongE
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredInstrClassD
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/InstrClassD
|
||||
add wave -noupdate -color Firebrick /testbench/dut/core/ifu/bpred/bpred/WrongPredInstrClassD
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BPPredWrongE
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BPPredWrongM
|
||||
add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF
|
||||
add wave -noupdate -expand -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/PCSrcE
|
||||
add wave -noupdate -expand -group {branch direction} -expand -group {branch outcome} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionE
|
||||
add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/TableDirPredictionF
|
||||
add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/MatchXF
|
||||
add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/DirPredictionWrongE
|
||||
add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE
|
||||
add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM
|
||||
add wave -noupdate -expand -group {branch direction} -expand -group conditions /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushE
|
||||
add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRF
|
||||
add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRD
|
||||
add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRE
|
||||
add wave -noupdate -expand -group {branch direction} -expand -group ghr /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRM
|
||||
add wave -noupdate -expand -group {branch direction} -expand -group ghr -color Orange /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRW
|
||||
add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE
|
||||
add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrF
|
||||
add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD
|
||||
add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextM
|
||||
add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE
|
||||
add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextF
|
||||
add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextD
|
||||
add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextE
|
||||
add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextM
|
||||
add wave -noupdate -expand -group {branch direction} -expand -group nextghr2 /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/GHRNextW
|
||||
add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrE
|
||||
add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/NewDirPredictionE
|
||||
add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexE
|
||||
add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/StallM
|
||||
add wave -noupdate -expand -group {branch direction} /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushM
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/IndexNextF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/PCNextF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/TargetPredictor/TableBTBPredictionF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/BPPredPCF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/SelBPPredF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/PredValidF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/BranchInstrF
|
||||
add wave -noupdate /testbench/dut/core/ifu/bpred/bpred/Predictor/DirPredictor/FlushD
|
||||
add wave -noupdate /testbench/dut/core/priv/priv/csr/counters/counters/HPMCOUNTER_REGW
|
||||
TreeUpdate [SetDefaultTree]
|
||||
WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {341201 ns} 1} {{Cursor 5} {116741 ns} 0}
|
||||
WaveRestoreCursors {{Cursor 2} {314596 ns} 1} {{Cursor 3} {314460 ns} 1} {{Cursor 4} {219681 ns} 1} {{Cursor 4} {1211181 ns} 1} {{Cursor 5} {158657 ns} 0}
|
||||
quietly wave cursor active 5
|
||||
configure wave -namecolwidth 250
|
||||
configure wave -valuecolwidth 194
|
||||
@ -620,4 +646,4 @@ configure wave -griddelta 40
|
||||
configure wave -timeline 0
|
||||
configure wave -timelineunits ns
|
||||
update
|
||||
WaveRestoreZoom {118528 ns} {128752 ns}
|
||||
WaveRestoreZoom {158482 ns} {158818 ns}
|
||||
|
||||
6
pipelined/src/cache/cacheLRU.sv
vendored
6
pipelined/src/cache/cacheLRU.sv
vendored
@ -81,8 +81,8 @@ module cacheLRU
|
||||
// expand HitWay as HitWay[3], {{2}{HitWay[2]}}, {{4}{HitWay[1]}, {{8{HitWay[0]}}, ...
|
||||
for(row = 0; row < LOGNUMWAYS; row++) begin
|
||||
localparam integer DuplicationFactor = 2**(LOGNUMWAYS-row-1);
|
||||
localparam integer StartIndex = NUMWAYS-2 - DuplicationFactor + 1;
|
||||
localparam integer EndIndex = NUMWAYS-2 - 2 * DuplicationFactor + 2;
|
||||
localparam StartIndex = NUMWAYS-2 - DuplicationFactor + 1;
|
||||
localparam EndIndex = NUMWAYS-2 - 2 * DuplicationFactor + 2;
|
||||
assign WayExpanded[StartIndex : EndIndex] = {{DuplicationFactor}{WayEncoded[row]}};
|
||||
end
|
||||
|
||||
@ -109,8 +109,6 @@ module cacheLRU
|
||||
for(s = NUMWAYS/2-1; s >= 0; s--) begin
|
||||
localparam int0 = (NUMWAYS/2-1-s)*2;
|
||||
localparam int1 = int0 + 1;
|
||||
//localparam int0 = s*2;
|
||||
//localparam int1 = int0 + 1;
|
||||
assign Intermediate[s] = CurrLRU[s] ? int1[LOGNUMWAYS-1:0] : int0[LOGNUMWAYS-1:0];
|
||||
end
|
||||
|
||||
|
||||
16
pipelined/src/cache/cacheway.sv
vendored
16
pipelined/src/cache/cacheway.sv
vendored
@ -55,11 +55,11 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
|
||||
output logic DirtyWay, // This way is dirty
|
||||
output logic [TAGLEN-1:0] TagWay); // THis way's tag if valid
|
||||
|
||||
localparam integer WORDSPERLINE = LINELEN/`XLEN;
|
||||
localparam integer BYTESPERLINE = LINELEN/8;
|
||||
localparam WORDSPERLINE = LINELEN/`XLEN;
|
||||
localparam BYTESPERLINE = LINELEN/8;
|
||||
localparam LOGWPL = $clog2(WORDSPERLINE);
|
||||
localparam LOGXLENBYTES = $clog2(`XLEN/8);
|
||||
localparam integer BYTESPERWORD = `XLEN/8;
|
||||
localparam BYTESPERWORD = `XLEN/8;
|
||||
|
||||
logic [NUMLINES-1:0] ValidBits;
|
||||
logic [NUMLINES-1:0] DirtyBits;
|
||||
@ -128,12 +128,12 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
|
||||
// Data Array
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
genvar words;
|
||||
genvar words;
|
||||
|
||||
localparam integer SRAMLEN = 128;
|
||||
localparam integer NUMSRAM = LINELEN/SRAMLEN;
|
||||
localparam integer SRAMLENINBYTES = SRAMLEN/8;
|
||||
localparam integer LOGNUMSRAM = $clog2(NUMSRAM);
|
||||
localparam SRAMLEN = 128;
|
||||
localparam NUMSRAM = LINELEN/SRAMLEN;
|
||||
localparam SRAMLENINBYTES = SRAMLEN/8;
|
||||
localparam LOGNUMSRAM = $clog2(NUMSRAM);
|
||||
|
||||
for(words = 0; words < NUMSRAM; words++) begin: word
|
||||
ram1p1rwbe #(.DEPTH(NUMLINES), .WIDTH(SRAMLEN)) CacheDataMem(.clk, .ce(CacheEn), .addr(CAdr),
|
||||
|
||||
4
pipelined/src/cache/subcachelineread.sv
vendored
4
pipelined/src/cache/subcachelineread.sv
vendored
@ -30,8 +30,8 @@
|
||||
`include "wally-config.vh"
|
||||
|
||||
module subcachelineread #(parameter LINELEN, WORDLEN,
|
||||
parameter MUXINTERVAL // The number of bits between mux. Set to 16 for I$ to support compressed. Set to `LLEN for D$
|
||||
)(
|
||||
parameter MUXINTERVAL )( // The number of bits between mux. Set to 16 for I$ to support compressed. Set to `LLEN for D$
|
||||
|
||||
input logic [$clog2(LINELEN/8) - $clog2(MUXINTERVAL/8) - 1 : 0] PAdr, // Physical address
|
||||
input logic [LINELEN-1:0] ReadDataLine,// Read data of the whole cacheline
|
||||
output logic [WORDLEN-1:0] ReadDataWord // read data of selected word.
|
||||
|
||||
@ -1 +0,0 @@
|
||||
/proj/wally/memory/ts1n28hpcpsvtb64x128m4sw_180a/VERILOG/ts1n28hpcpsvtb64x128m4sw_180a_tt1v25c.v
|
||||
@ -30,10 +30,10 @@
|
||||
`include "wally-config.vh"
|
||||
|
||||
module ahbcacheinterface #(
|
||||
parameter integer BEATSPERLINE, // Number of AHBW words (beats) in cacheline
|
||||
parameter integer AHBWLOGBWPL, // Log2 of ^
|
||||
parameter integer LINELEN, // Number of bits in cacheline
|
||||
parameter integer LLENPOVERAHBW // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
|
||||
parameter BEATSPERLINE, // Number of AHBW words (beats) in cacheline
|
||||
parameter AHBWLOGBWPL, // Log2 of ^
|
||||
parameter LINELEN, // Number of bits in cacheline
|
||||
parameter LLENPOVERAHBW // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
|
||||
)(
|
||||
input logic HCLK, HRESETn,
|
||||
// bus interface controls
|
||||
@ -72,12 +72,12 @@ module ahbcacheinterface #(
|
||||
output logic BusCommitted); // Bus is busy with an in flight memory operation and it is not safe to take an interrupt
|
||||
|
||||
|
||||
localparam integer BeatCountThreshold = BEATSPERLINE - 1; // Largest beat index
|
||||
logic [`PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation
|
||||
logic [AHBWLOGBWPL-1:0] BeatCountDelayed; // Beat within the cache line in the second (Data) cache stage
|
||||
logic CaptureEn; // Enable updating the Fetch buffer with valid data from HRDATA
|
||||
logic [`AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s
|
||||
logic [`AHBW-1:0] PreHWDATA; // AHB Address phase write data
|
||||
localparam BeatCountThreshold = BEATSPERLINE - 1; // Largest beat index
|
||||
logic [`PA_BITS-1:0] LocalHADDR; // Address after selecting between cached and uncached operation
|
||||
logic [AHBWLOGBWPL-1:0] BeatCountDelayed; // Beat within the cache line in the second (Data) cache stage
|
||||
logic CaptureEn; // Enable updating the Fetch buffer with valid data from HRDATA
|
||||
logic [`AHBW/8-1:0] BusByteMaskM; // Byte enables within a word. For cache request all 1s
|
||||
logic [`AHBW-1:0] PreHWDATA; // AHB Address phase write data
|
||||
|
||||
genvar index;
|
||||
|
||||
|
||||
@ -32,8 +32,8 @@
|
||||
|
||||
// HCLK and clk must be the same clock!
|
||||
module buscachefsm #(
|
||||
parameter integer BeatCountThreshold, // Largest beat index
|
||||
parameter integer AHBWLOGBWPL // Log2 of BEATSPERLINE
|
||||
parameter BeatCountThreshold, // Largest beat index
|
||||
parameter AHBWLOGBWPL // Log2 of BEATSPERLINE
|
||||
)(
|
||||
input logic HCLK,
|
||||
input logic HRESETn,
|
||||
|
||||
@ -49,17 +49,25 @@ module ram1p1rwbe #(parameter DEPTH=128, WIDTH=256) (
|
||||
// ***************************************************************************
|
||||
// TRUE SRAM macro
|
||||
// ***************************************************************************
|
||||
if (`USE_SRAM == 1) begin
|
||||
if (`USE_SRAM == 1 && WIDTH == 128 && `XLEN == 64) begin
|
||||
genvar index;
|
||||
// 64 x 128-bit SRAM
|
||||
// check if the size is ok, complain if not***
|
||||
logic [WIDTH-1:0] BitWriteMask;
|
||||
for (index=0; index < WIDTH; index++)
|
||||
assign BitWriteMask[index] = bwe[index/8];
|
||||
TS1N28HPCPSVTB64X128M4SW sram(
|
||||
.CLK(clk), .CEB(~ce), .WEB(~we),
|
||||
.A(addr), .D(din),
|
||||
.BWEB(~BitWriteMask), .Q(dout));
|
||||
// 64 x 128-bit SRAM
|
||||
logic [WIDTH-1:0] BitWriteMask;
|
||||
for (index=0; index < WIDTH; index++)
|
||||
assign BitWriteMask[index] = bwe[index/8];
|
||||
ram1p1rwbe_64x128 sram1A (.CLK(clk), .CEB(~ce), .WEB(~we),
|
||||
.A(addr), .D(din),
|
||||
.BWEB(~BitWriteMask), .Q(dout));
|
||||
|
||||
end else if (`USE_SRAM == 1 && WIDTH == 44 && `XLEN == 64) begin
|
||||
genvar index;
|
||||
// 64 x 44-bit SRAM
|
||||
logic [WIDTH-1:0] BitWriteMask;
|
||||
for (index=0; index < WIDTH; index++)
|
||||
assign BitWriteMask[index] = bwe[index/8];
|
||||
ram1p1rwbe_64x44 sram1B (.CLK(clk), .CEB(~ce), .WEB(~we),
|
||||
.A(addr), .D(din),
|
||||
.BWEB(~BitWriteMask), .Q(dout));
|
||||
|
||||
// ***************************************************************************
|
||||
// READ first SRAM model
|
||||
|
||||
40
pipelined/src/generic/mem/ram1p1rwbe_64x128.sv
Executable file
40
pipelined/src/generic/mem/ram1p1rwbe_64x128.sv
Executable file
@ -0,0 +1,40 @@
|
||||
///////////////////////////////////////////
|
||||
// ram1p1rwbe_64x128.sv
|
||||
//
|
||||
// Written: james.stine@okstate.edu 28 January 2023
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: RAM wrapper for instantiating RAM IP
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module ram1p1rwbe_64x128(
|
||||
input logic CLK,
|
||||
input logic CEB,
|
||||
input logic WEB,
|
||||
input logic [5:0] A,
|
||||
input logic [127:0] D,
|
||||
input logic [127:0] BWEB,
|
||||
output logic [127:0] Q
|
||||
);
|
||||
|
||||
// replace "generic64x128RAM" with "TS1N..64X128.." module from your memory vendor
|
||||
generic64x128RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q);
|
||||
|
||||
endmodule
|
||||
@ -1,16 +1,11 @@
|
||||
///////////////////////////////////////////
|
||||
// bmu.sv
|
||||
// ram1p1rwbe_64x44.sv
|
||||
//
|
||||
// Written: kekim@g.hmc.edu, David_Harris@hmc.edu 20 January 2023
|
||||
// Written: james.stine@okstate.edu 28 January 2023
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Bit manipulation extensions Zba, Zbb, Zbc, Zbs
|
||||
// Single-cycle operation in Execute stage
|
||||
// Purpose: RAM wrapper for instantiating RAM IP
|
||||
//
|
||||
// Documentation: n/a
|
||||
// See RISC-V Bit-Manipulation ISA-extensions
|
||||
// Version 1.0.0-38-g865e7a7, 2021-06-28: Release candidate
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
@ -29,17 +24,17 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module bmu(
|
||||
input logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // inputs A and B from IEU forwarding mux output
|
||||
input logic [31:0] InstrD, // instruction
|
||||
output logic BMUE, // bit manipulation instruction
|
||||
output logic [`XLEN-1:0] BMUResultE // bit manipulation result
|
||||
module ram1p1rwbe_64x44(
|
||||
input logic CLK,
|
||||
input logic CEB,
|
||||
input logic WEB,
|
||||
input logic [5:0] A,
|
||||
input logic [127:0] D,
|
||||
input logic [127:0] BWEB,
|
||||
output logic [127:0] Q
|
||||
);
|
||||
|
||||
// replace "generic64x44RAM" with "TS1N..64X44.." module from your memory vendor
|
||||
generic64x44RAM sramIP (.CLK, .CEB, .WEB, .A, .D, .BWEB, .Q);
|
||||
|
||||
|
||||
endmodule // mdu
|
||||
|
||||
|
||||
endmodule
|
||||
@ -1,86 +0,0 @@
|
||||
///////////////////////////////////////////
|
||||
// ram2p1r1wb
|
||||
//
|
||||
// Written: Ross Thomposn
|
||||
// Email: ross1728@gmail.com
|
||||
// Created: February 14, 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Behavioral model of two port SRAM. While this is synthesizable it will produce a flip flop based memory which
|
||||
// behaves with the timing of an SRAM typical of GF 14nm, 32nm, and 45nm.
|
||||
//
|
||||
//
|
||||
// to preload this memory we can use the following command
|
||||
// in modelsim's do file.
|
||||
// mem load -infile <relative path to the text file > -format <bin|hex> <hierarchy to the memory.>
|
||||
// example
|
||||
// mem load -infile twoBitPredictor.txt -format bin testbench/dut/core/ifu/bpred/DirPredictor/memory/memory
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module ram2p1r1wb #(parameter DEPTH = 10, WIDTH = 2) (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
|
||||
// port 1 is read only
|
||||
input logic [DEPTH-1:0] ra1,
|
||||
output logic [WIDTH-1:0] rd1,
|
||||
input logic ren1,
|
||||
|
||||
// port 2 is write only
|
||||
input logic [DEPTH-1:0] wa2,
|
||||
input logic [WIDTH-1:0] wd2,
|
||||
input logic wen2,
|
||||
input logic [WIDTH-1:0] bwe2
|
||||
);
|
||||
|
||||
|
||||
logic [DEPTH-1:0] ra1q, wa2q;
|
||||
logic wen2q;
|
||||
logic [WIDTH-1:0] wd2q;
|
||||
|
||||
logic [WIDTH-1:0] mem[2**DEPTH-1:0];
|
||||
logic [WIDTH-1:0] bwe;
|
||||
|
||||
|
||||
// SRAMs address busses are always registered first
|
||||
// *** likely issued DH and RT 12/20/22
|
||||
// wrong enable for write port registers
|
||||
// prefer to code read like ram1p1rw
|
||||
// prefer not to have two-cycle write latency
|
||||
// will require branch predictor changes
|
||||
|
||||
flopenr #(DEPTH) ra1Reg(clk, reset, ren1, ra1, ra1q);
|
||||
flopenr #(DEPTH) wa2Reg(clk, reset, ren1, wa2, wa2q);
|
||||
flopr #(1) wen2Reg(clk, reset, wen2, wen2q);
|
||||
flopenr #(WIDTH) wd2Reg(clk, reset, ren1, wd2, wd2q);
|
||||
|
||||
// read port
|
||||
assign rd1 = mem[ra1q];
|
||||
|
||||
// write port
|
||||
assign bwe = {WIDTH{wen2q}} & bwe2;
|
||||
always_ff @(posedge clk)
|
||||
mem[wa2q] <= wd2q & bwe | mem[wa2q] & ~bwe;
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
@ -1,8 +1,8 @@
|
||||
///////////////////////////////////////////
|
||||
// 1 port sram.
|
||||
// 2 port sram.
|
||||
//
|
||||
// Written: ross1728@gmail.com May 3, 2021
|
||||
// Basic sram with 1 read write port.
|
||||
// Two port SRAM 1 read port and 1 write port.
|
||||
// When clk rises Addr and LineWriteData are sampled.
|
||||
// Following the clk edge read data is output from the sampled Addr.
|
||||
// Write
|
||||
@ -31,7 +31,7 @@
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module ram2p1r1wbefix #(parameter DEPTH=128, WIDTH=256) (
|
||||
module ram2p1r1wbe #(parameter DEPTH=128, WIDTH=256) (
|
||||
input logic clk,
|
||||
input logic ce1, ce2,
|
||||
input logic [$clog2(DEPTH)-1:0] ra1,
|
||||
@ -59,13 +59,13 @@ module ram2p1r1wbefix #(parameter DEPTH=128, WIDTH=256) (
|
||||
|
||||
// Write divided into part for bytes and part for extra msbs
|
||||
if(WIDTH >= 8)
|
||||
always_ff @(posedge clk)
|
||||
always @(posedge clk)
|
||||
if (ce2 & we2)
|
||||
for(i = 0; i < WIDTH/8; i++)
|
||||
if(bwe2[i]) mem[wa2][i*8 +: 8] <= #1 wd2[i*8 +: 8];
|
||||
|
||||
if (WIDTH%8 != 0) // handle msbs if width not a multiple of 8
|
||||
always_ff @(posedge clk)
|
||||
always @(posedge clk)
|
||||
if (ce2 & we2 & bwe2[WIDTH/8])
|
||||
mem[wa2][WIDTH-1:WIDTH-WIDTH%8] <= #1 wd2[WIDTH-1:WIDTH-WIDTH%8];
|
||||
|
||||
48
pipelined/src/generic/mem/ram2p1r1wbe_1024x69.sv
Executable file
48
pipelined/src/generic/mem/ram2p1r1wbe_1024x69.sv
Executable file
@ -0,0 +1,48 @@
|
||||
///////////////////////////////////////////
|
||||
// ram2p1rwbe_1024x69.sv
|
||||
//
|
||||
// Written: james.stine@okstate.edu 28 January 2023
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: RAM wrapper for instantiating RAM IP
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module ram2p1r1wbe_1024x69(
|
||||
input logic CLKA,
|
||||
input logic CLKB,
|
||||
input logic CEBA,
|
||||
input logic CEBB,
|
||||
input logic WEBA,
|
||||
input logic WEBB,
|
||||
input logic [9:0] AA,
|
||||
input logic [9:0] AB,
|
||||
input logic [68:0] DA,
|
||||
input logic [68:0] DB,
|
||||
input logic [68:0] BWEBA,
|
||||
input logic [68:0] BWEBB,
|
||||
output logic [68:0] QA,
|
||||
output logic [68:0] QB
|
||||
);
|
||||
|
||||
// replace "generic1024x69RAM" with "TSDN..1024X69.." module from your memory vendor
|
||||
generic1024x69RAM sramIP (.CLKA, .CLKB, .CEBA, .CEBB, .WEBA, .WEBB,
|
||||
.AA, .AB, .DA, .DB, .BWEBA, .BWEBB, .QA, .QB);
|
||||
|
||||
endmodule
|
||||
38
pipelined/src/generic/mem/rom1p1r_128x32.sv
Executable file
38
pipelined/src/generic/mem/rom1p1r_128x32.sv
Executable file
@ -0,0 +1,38 @@
|
||||
///////////////////////////////////////////
|
||||
// rom1p1r_128x32.sv
|
||||
//
|
||||
// Written: james.stine@okstate.edu 28 January 2023
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: RAM wrapper for instantiating RAM IP
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
module rom1p1r_128x32(
|
||||
input logic CLK,
|
||||
input logic CEB,
|
||||
input logic [6:0] A,
|
||||
output logic [31:0] Q
|
||||
);
|
||||
|
||||
// replace "generic128x32ROM" with "TS3N..128X32.." module from your memory vendor
|
||||
generic64x128ROM sramIP (.CLK, .CEB, .A, .Q);
|
||||
|
||||
endmodule
|
||||
|
||||
@ -200,7 +200,7 @@ module controller(
|
||||
// Fences
|
||||
// Ordinary fence is presently a nop
|
||||
// fence.i flushes the D$ and invalidates the I$ if Zifencei is supported and I$ is implemented
|
||||
if (`ZIFENCEI_SUPPORTED & `ICACHE) begin:fencei
|
||||
if (`ZIFENCEI_SUPPORTED & `ICACHE_SUPPORTED) begin:fencei
|
||||
logic FenceID;
|
||||
assign FenceID = FenceXD & (Funct3D == 3'b001); // is it a FENCE.I instruction?
|
||||
assign InvalidateICacheD = FenceID;
|
||||
@ -249,5 +249,5 @@ module controller(
|
||||
|
||||
// the synchronous DTIM cannot read immediately after write
|
||||
// a cache cannot read or write immediately after a write
|
||||
assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & `DCACHE)) | (|AtomicD));
|
||||
assign StoreStallD = MemRWE[0] & ((MemRWD[1] | (MemRWD[0] & `DCACHE_SUPPORTED)) | (|AtomicD));
|
||||
endmodule
|
||||
|
||||
@ -48,7 +48,6 @@ module datapath (
|
||||
output logic [1:0] FlagsE, // Comparison flags ({eq, lt})
|
||||
output logic [`XLEN-1:0] IEUAdrE, // Address computed by ALU
|
||||
output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU sources before the mux chooses between them and PCE to put in srcA/B
|
||||
input logic BMUE, // Bit manipulation instruction
|
||||
// Memory stage signals
|
||||
input logic StallM, FlushM, // Stall, flush Memory stage
|
||||
input logic FWriteIntM, FCvtIntW, // FPU writes integer register file, FPU converts float to int
|
||||
@ -64,7 +63,6 @@ module datapath (
|
||||
input logic [`XLEN-1:0] ReadDataW, // Read data from LSU
|
||||
input logic [`XLEN-1:0] CSRReadValW, // CSR read result
|
||||
input logic [`XLEN-1:0] MDUResultW, // MDU (Multiply/divide unit) result
|
||||
input logic [`XLEN-1:0] BMUResultE, // bit manipulation unit result
|
||||
input logic [`XLEN-1:0] FIntDivResultW, // FPU's integer divide result
|
||||
// Hazard Unit signals
|
||||
output logic [4:0] Rs1D, Rs2D, Rs1E, Rs2E, // Register sources to read in Decode or Execute stage
|
||||
@ -81,7 +79,6 @@ module datapath (
|
||||
logic [`XLEN-1:0] ImmExtE; // Extended immediate in Execute stage
|
||||
logic [`XLEN-1:0] SrcAE, SrcBE; // ALU operands
|
||||
logic [`XLEN-1:0] ALUResultE, AltResultE, IEUResultE; // ALU result, Alternative result (ImmExtE or PC+4), result of execution stage
|
||||
logic [`XLEN-1:0] IEUBResultE; // IEUResultE before optional bit manipulation mux
|
||||
// Memory stage signals
|
||||
logic [`XLEN-1:0] IEUResultM; // Result from execution stage
|
||||
logic [`XLEN-1:0] IFResultM; // Result from either IEU or single-cycle FPU op writing an integer register
|
||||
@ -114,10 +111,7 @@ module datapath (
|
||||
mux2 #(`XLEN) srcbmux(ForwardedSrcBE, ImmExtE, ALUSrcBE, SrcBE);
|
||||
alu #(`XLEN) alu(SrcAE, SrcBE, ALUControlE, Funct3E, ALUResultE, IEUAdrE);
|
||||
mux2 #(`XLEN) altresultmux(ImmExtE, PCLinkE, JumpE, AltResultE);
|
||||
mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUBResultE);
|
||||
if (`B_SUPPORTED)
|
||||
mux2 #(`XLEN) bmuresultmux(IEUResultE, BMUResultE, BMUE, IEUResultE);
|
||||
else assign IEUResultE = IEUBResultE;
|
||||
mux2 #(`XLEN) ieuresultmux(ALUResultE, AltResultE, ALUResultSrcE, IEUResultE);
|
||||
|
||||
// Memory stage pipeline register
|
||||
flopenrc #(`XLEN) SrcAMReg(clk, reset, FlushM, ~StallM, SrcAE, SrcAM);
|
||||
|
||||
@ -43,7 +43,6 @@ module ieu (
|
||||
output logic IntDivE, W64E, // Integer divide, RV64 W-type instruction
|
||||
output logic [2:0] Funct3E, // Funct3 instruction field
|
||||
output logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE, // ALU src inputs before the mux choosing between them and PCE to put in srcA/B
|
||||
input logic BMUE, // This is a bit manipulation instruction
|
||||
output logic [4:0] RdE, // Destination register
|
||||
// Memory stage signals
|
||||
input logic SquashSCW, // Squash store conditional, from LSU
|
||||
@ -60,7 +59,6 @@ module ieu (
|
||||
input logic [`XLEN-1:0] FIntDivResultW, // Integer divide result from FPU fdivsqrt)
|
||||
input logic [`XLEN-1:0] CSRReadValW, // CSR read value,
|
||||
input logic [`XLEN-1:0] MDUResultW, // multiply/divide unit result
|
||||
input logic [`XLEN-1:0] BMUResultE, // bit manipulation unit result
|
||||
input logic [`XLEN-1:0] FCvtIntResW, // FPU's float to int conversion result
|
||||
input logic FCvtIntW, // FPU converts float to int
|
||||
output logic [4:0] RdW, // Destination register
|
||||
@ -105,10 +103,10 @@ module ieu (
|
||||
datapath dp(
|
||||
.clk, .reset, .ImmSrcD, .InstrD, .StallE, .FlushE, .ForwardAE, .ForwardBE,
|
||||
.ALUControlE, .Funct3E, .ALUSrcAE, .ALUSrcBE, .ALUResultSrcE, .JumpE, .BranchSignedE,
|
||||
.PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE, .BMUE,
|
||||
.PCE, .PCLinkE, .FlagsE, .IEUAdrE, .ForwardedSrcAE, .ForwardedSrcBE,
|
||||
.StallM, .FlushM, .FWriteIntM, .FIntResM, .SrcAM, .WriteDataM, .FCvtIntW,
|
||||
.StallW, .FlushW, .RegWriteW, .IntDivW, .SquashSCW, .ResultSrcW, .ReadDataW, .FCvtIntResW,
|
||||
.CSRReadValW, .MDUResultW, .BMUResultE, .FIntDivResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW);
|
||||
.CSRReadValW, .MDUResultW, .FIntDivResultW, .Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW);
|
||||
|
||||
forward fw(
|
||||
.Rs1D, .Rs2D, .Rs1E, .Rs2E, .RdE, .RdM, .RdW,
|
||||
|
||||
@ -1,114 +0,0 @@
|
||||
///////////////////////////////////////////
|
||||
// ram2p1r1wb
|
||||
//
|
||||
// Written: Ross Thomposn
|
||||
// Email: ross1728@gmail.com
|
||||
// Created: February 15, 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: BTB model. Outputs type of instruction (currently 1 hot encoded. Probably want
|
||||
// to encode to reduce storage), valid, target PC.
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module BTBPredictor
|
||||
#(parameter int Depth = 10
|
||||
)
|
||||
(input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallE,
|
||||
input logic [`XLEN-1:0] LookUpPC,
|
||||
output logic [`XLEN-1:0] TargetPC,
|
||||
output logic [3:0] InstrClass,
|
||||
output logic Valid,
|
||||
// update
|
||||
input logic UpdateEN,
|
||||
input logic [`XLEN-1:0] UpdatePC,
|
||||
input logic [`XLEN-1:0] UpdateTarget,
|
||||
input logic [3:0] UpdateInstrClass,
|
||||
input logic UpdateInvalid
|
||||
);
|
||||
|
||||
localparam TotalDepth = 2 ** Depth;
|
||||
logic [TotalDepth-1:0] ValidBits;
|
||||
logic [Depth-1:0] LookUpPCIndex, UpdatePCIndex, LookUpPCIndexQ, UpdatePCIndexQ;
|
||||
logic UpdateENQ;
|
||||
|
||||
|
||||
// hashing function for indexing the PC
|
||||
// We have Depth bits to index, but XLEN bits as the input.
|
||||
// bit 0 is always 0, bit 1 is 0 if using 4 byte instructions, but is not always 0 if
|
||||
// using compressed instructions. XOR bit 1 with the MSB of index.
|
||||
assign UpdatePCIndex = {UpdatePC[Depth+1] ^ UpdatePC[1], UpdatePC[Depth:2]};
|
||||
assign LookUpPCIndex = {LookUpPC[Depth+1] ^ LookUpPC[1], LookUpPC[Depth:2]};
|
||||
|
||||
|
||||
flopenr #(Depth) UpdatePCIndexReg(.clk(clk),
|
||||
.reset(reset),
|
||||
.en(~StallE),
|
||||
.d(UpdatePCIndex),
|
||||
.q(UpdatePCIndexQ));
|
||||
|
||||
// The valid bit must be resetable.
|
||||
always_ff @ (posedge clk) begin
|
||||
if (reset) begin
|
||||
ValidBits <= #1 {TotalDepth{1'b0}};
|
||||
end else
|
||||
if (UpdateENQ) begin
|
||||
ValidBits[UpdatePCIndexQ] <= #1 ~ UpdateInvalid;
|
||||
end
|
||||
end
|
||||
assign Valid = ValidBits[LookUpPCIndexQ];
|
||||
|
||||
|
||||
flopenr #(1) UpdateENReg(.clk(clk),
|
||||
.reset(reset),
|
||||
.en(~StallF),
|
||||
.d(UpdateEN),
|
||||
.q(UpdateENQ));
|
||||
|
||||
|
||||
flopenr #(Depth) LookupPCIndexReg(.clk(clk),
|
||||
.reset(reset),
|
||||
.en(~StallF),
|
||||
.d(LookUpPCIndex),
|
||||
.q(LookUpPCIndexQ));
|
||||
|
||||
|
||||
|
||||
// the BTB contains the target address.
|
||||
// Another optimization may be using a PC relative address.
|
||||
// *** need to add forwarding.
|
||||
|
||||
// *** optimize for byte write enables
|
||||
// *** switch to ram2p1r1wbefix
|
||||
ram2p1r1wb #(Depth, `XLEN+4) memory(.clk(clk),
|
||||
.reset(reset),
|
||||
.ra1(LookUpPCIndex),
|
||||
.rd1({{InstrClass, TargetPC}}),
|
||||
.ren1(~StallF),
|
||||
.wa2(UpdatePCIndex),
|
||||
.wd2({UpdateInstrClass, UpdateTarget}),
|
||||
.wen2(UpdateEN),
|
||||
.bwe2({4'hF, {`XLEN{1'b1}}})); // *** definitely not right.
|
||||
|
||||
|
||||
endmodule
|
||||
@ -1,86 +0,0 @@
|
||||
///////////////////////////////////////////
|
||||
// RASPredictor.sv
|
||||
//
|
||||
// Written: Ross Thomposn
|
||||
// Email: ross1728@gmail.com
|
||||
// Created: February 15, 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: 2 bit saturating counter predictor with parameterized table depth.
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module RASPredictor
|
||||
#(parameter int StackSize = 16
|
||||
)
|
||||
(input logic clk,
|
||||
input logic reset,
|
||||
input logic PopF,
|
||||
output logic [`XLEN-1:0] RASPCF,
|
||||
input logic [3:0] WrongPredInstrClassD,
|
||||
input logic [3:0] InstrClassD,
|
||||
input logic PushE,
|
||||
input logic incr,
|
||||
input logic [`XLEN-1:0] PCLinkE
|
||||
);
|
||||
|
||||
// *** need to update so it either doesn't push until the memory stage
|
||||
// or need to repair flushed push.
|
||||
// *** need to repair popped and then flushed returns.
|
||||
logic CounterEn;
|
||||
localparam Depth = $clog2(StackSize);
|
||||
|
||||
logic [Depth-1:0] PtrD, PtrQ, PtrP1, PtrM1;
|
||||
logic [StackSize-1:0] [`XLEN-1:0] memory;
|
||||
integer index;
|
||||
|
||||
assign CounterEn = PopF | PushE | incr | WrongPredInstrClassD[2];
|
||||
|
||||
assign PtrD = PopF | InstrClassD[2] ? PtrM1 : PtrP1;
|
||||
|
||||
assign PtrM1 = PtrQ - 1'b1;
|
||||
assign PtrP1 = PtrQ + 1'b1;
|
||||
// may have to handle a PushE and an incr at the same time.
|
||||
// *** what happens if jal is executing and there is a return being flushed in Decode?
|
||||
|
||||
flopenr #(Depth) PTR(.clk(clk),
|
||||
.reset(reset),
|
||||
.en(CounterEn),
|
||||
.d(PtrD),
|
||||
.q(PtrQ));
|
||||
|
||||
// RAS must be reset.
|
||||
always_ff @ (posedge clk) begin
|
||||
if(reset) begin
|
||||
for(index=0; index<StackSize; index++)
|
||||
memory[index] <= {`XLEN{1'b0}};
|
||||
end else if(PushE) begin
|
||||
memory[PtrP1] <= #1 PCLinkE;
|
||||
end
|
||||
end
|
||||
|
||||
assign RASPCF = memory[PtrQ];
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
@ -1,237 +0,0 @@
|
||||
///////////////////////////////////////////
|
||||
// bpred.sv
|
||||
//
|
||||
// Written: Ross Thomposn ross1728@gmail.com
|
||||
// Created: 12 February 2021
|
||||
// Modified: 19 January 2023
|
||||
//
|
||||
// Purpose: Branch direction prediction and jump/branch target prediction.
|
||||
// Prediction made during the fetch stage and corrected in the execution stage.
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module bpred (
|
||||
input logic clk, reset,
|
||||
input logic StallF, StallD, StallE, StallM, StallW,
|
||||
input logic FlushD, FlushE, FlushM, FlushW,
|
||||
// Fetch stage
|
||||
// the prediction
|
||||
input logic [31:0] InstrD, // Decompressed decode stage instruction. Used to decode instruction class
|
||||
input logic [`XLEN-1:0] PCNextF, // Next Fetch Address
|
||||
input logic [`XLEN-1:0] PCPlus2or4F, // PCF+2/4
|
||||
output logic [`XLEN-1:0] PCNext1F, // Branch Predictor predicted or corrected fetch address on miss prediction
|
||||
output logic [`XLEN-1:0] NextValidPCE, // Address of next valid instruction after the instruction in the Memory stage
|
||||
|
||||
// Update Predictor
|
||||
input logic [`XLEN-1:0] PCF, // Fetch stage instruction address
|
||||
input logic [`XLEN-1:0] PCD, // Decode stage instruction address. Also the address the branch predictor took
|
||||
input logic [`XLEN-1:0] PCE, // Execution stage instruction address
|
||||
input logic [`XLEN-1:0] PCM, // Memory stage instruction address
|
||||
|
||||
// Branch and jump outcome
|
||||
input logic PCSrcE, // Executation stage branch is taken
|
||||
input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address
|
||||
input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address)
|
||||
output logic [3:0] InstrClassM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
|
||||
|
||||
// Report branch prediction status
|
||||
output logic BPPredWrongE, // Prediction is wrong
|
||||
output logic DirPredictionWrongM, // Prediction direction is wrong
|
||||
output logic BTBPredPCWrongM, // Prediction target wrong
|
||||
output logic RASPredPCWrongM, // RAS prediction is wrong
|
||||
output logic PredictionInstrClassWrongM // Class prediction is wrong
|
||||
);
|
||||
|
||||
logic BTBValidF;
|
||||
logic [1:0] DirPredictionF;
|
||||
|
||||
logic [3:0] PredInstrClassF, PredInstrClassD, PredInstrClassE;
|
||||
logic [`XLEN-1:0] BTBPredPCF, RASPCF;
|
||||
logic TargetWrongE;
|
||||
logic FallThroughWrongE;
|
||||
logic PredictionPCWrongE;
|
||||
logic PredictionInstrClassWrongE;
|
||||
logic [3:0] InstrClassD, InstrClassE, InstrClassW;
|
||||
logic DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;
|
||||
|
||||
logic SelBPPredF;
|
||||
logic [`XLEN-1:0] BPPredPCF;
|
||||
logic BPPredWrongM;
|
||||
logic [`XLEN-1:0] PCNext0F;
|
||||
logic [`XLEN-1:0] PCCorrectE;
|
||||
logic [3:0] WrongPredInstrClassD;
|
||||
|
||||
// Part 1 branch direction prediction
|
||||
// look into the 2 port Sram model. something is wrong.
|
||||
if (`BPTYPE == "BPTWOBIT") begin:Predictor
|
||||
twoBitPredictor DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
|
||||
.PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
|
||||
.BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
|
||||
|
||||
end else if (`BPTYPE == "BPGLOBAL") begin:Predictor
|
||||
globalhistory DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
|
||||
.PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
|
||||
.BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
|
||||
|
||||
end else if (`BPTYPE == "BPSPECULATIVEGLOBAL") begin:Predictor
|
||||
speculativeglobalhistory #(10) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
|
||||
.PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
|
||||
.BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]),
|
||||
.BranchInstrW(InstrClassW[0]), .PCSrcE);
|
||||
|
||||
end else if (`BPTYPE == "BPGSHARE") begin:Predictor
|
||||
gshare DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
|
||||
.PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
|
||||
.BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
|
||||
|
||||
end else if (`BPTYPE == "BPSPECULATIVEGSHARE") begin:Predictor
|
||||
speculativegshare DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
|
||||
.PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
|
||||
.BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]),
|
||||
.BranchInstrW(InstrClassW[0]), .WrongPredInstrClassD, .PCSrcE);
|
||||
|
||||
end else if (`BPTYPE == "BPLOCALPAg") begin:Predictor
|
||||
// *** Fix me
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
localHistoryPredictor DirPredictor(.clk,
|
||||
.reset, .StallF, .StallE,
|
||||
.LookUpPC(PCNextF),
|
||||
.Prediction(DirPredictionF),
|
||||
// update
|
||||
.UpdatePC(PCE),
|
||||
.UpdateEN(InstrClassE[0] & ~StallE),
|
||||
.PCSrcE,
|
||||
.UpdatePrediction(InstrClassE[0]));
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
end
|
||||
|
||||
|
||||
// this predictor will have two pieces of data,
|
||||
// 1) A direction (1 = Taken, 0 = Not Taken)
|
||||
// 2) Any information which is necessary for the predictor to build its next state.
|
||||
// For a 2 bit table this is the prediction count.
|
||||
assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & BTBValidF) |
|
||||
PredInstrClassF[2] |
|
||||
(PredInstrClassF[1] & BTBValidF) ;
|
||||
|
||||
// Part 2 Branch target address prediction
|
||||
// *** For now the BTB will house the direct and indirect targets
|
||||
|
||||
// *** getting to many false positivies from the BTB, we need a partial TAG to reduce this.
|
||||
BTBPredictor TargetPredictor(.clk(clk),
|
||||
.reset(reset),
|
||||
.*, // Stalls and flushes
|
||||
.LookUpPC(PCNextF),
|
||||
.TargetPC(BTBPredPCF),
|
||||
.InstrClass(PredInstrClassF),
|
||||
.Valid(BTBValidF),
|
||||
// update
|
||||
.UpdateEN((|InstrClassE | (PredictionInstrClassWrongE)) & ~StallE),
|
||||
.UpdatePC(PCE),
|
||||
.UpdateTarget(IEUAdrE),
|
||||
.UpdateInvalid(PredictionInstrClassWrongE),
|
||||
.UpdateInstrClass(InstrClassE));
|
||||
|
||||
// Part 3 RAS
|
||||
// *** need to add the logic to restore RAS on flushes. We will use incr for this.
|
||||
// *** needs to include flushX
|
||||
RASPredictor RASPredictor(.clk(clk),
|
||||
.reset(reset),
|
||||
.PopF(PredInstrClassF[2] & ~StallF),
|
||||
.WrongPredInstrClassD,
|
||||
.InstrClassD,
|
||||
.RASPCF,
|
||||
.PushE(InstrClassE[3] & ~StallE),
|
||||
.incr(1'b0),
|
||||
.PCLinkE);
|
||||
|
||||
assign BPPredPCF = PredInstrClassF[2] ? RASPCF : BTBPredPCF;
|
||||
|
||||
// the branch predictor needs a compact decoding of the instruction class.
|
||||
assign InstrClassD[3] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5
|
||||
assign InstrClassD[2] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5
|
||||
assign InstrClassD[1] = (InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) != 5'h01 & (InstrD[11:7] & 5'h1B) != 5'h01) | // jump register, but not return
|
||||
(InstrD[6:0] == 7'h6F & (InstrD[11:7] & 5'h1B) != 5'h01); // jump, RD != x1 or x5
|
||||
assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch
|
||||
flopenrc #(4) InstrClassRegE(clk, reset, FlushE, ~StallE, InstrClassD, InstrClassE);
|
||||
flopenrc #(4) InstrClassRegM(clk, reset, FlushM, ~StallM, InstrClassE, InstrClassM);
|
||||
flopenrc #(4) InstrClassRegW(clk, reset, FlushW, ~StallW, InstrClassM, InstrClassW);
|
||||
flopenrc #(1) BPPredWrongMReg(clk, reset, FlushM, ~StallM, BPPredWrongE, BPPredWrongM);
|
||||
|
||||
// branch predictor
|
||||
flopenrc #(4) BPPredWrongRegM(clk, reset, FlushM, ~StallM,
|
||||
{DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE, PredictionInstrClassWrongE},
|
||||
{DirPredictionWrongM, BTBPredPCWrongM, RASPredPCWrongM, PredictionInstrClassWrongM});
|
||||
|
||||
// pipeline the class
|
||||
flopenrc #(4) PredInstrClassRegD(clk, reset, FlushD, ~StallD, PredInstrClassF, PredInstrClassD);
|
||||
flopenrc #(4) PredInstrClassRegE(clk, reset, FlushE, ~StallE, PredInstrClassD, PredInstrClassE);
|
||||
|
||||
// Check the prediction
|
||||
// first check if the target or fallthrough address matches what was predicted.
|
||||
assign TargetWrongE = IEUAdrE != PCD;
|
||||
assign FallThroughWrongE = PCLinkE != PCD;
|
||||
// If the target is taken check the target rather than fallthrough. The instruction needs to be a branch if PCSrcE is selected
|
||||
// Remember the bpred can incorrectly predict a non cfi instruction as a branch taken. If the real instruction is non cfi
|
||||
// it must have selected the fall through.
|
||||
assign PredictionPCWrongE = (PCSrcE & (|InstrClassE) ? TargetWrongE : FallThroughWrongE);
|
||||
|
||||
// The branch direction also need to checked.
|
||||
// However if the direction is wrong then the pc will be wrong. This is only relavent to checking the
|
||||
// accuracy of the direciton prediction.
|
||||
//assign DirPredictionWrongE = (BPPredE[1] ^ PCSrcE) & InstrClassE[0];
|
||||
|
||||
// Finally we need to check if the class is wrong. When the class is wrong the BTB needs to be updated.
|
||||
// Also we want to track this in a performance counter.
|
||||
assign PredictionInstrClassWrongE = InstrClassE != PredInstrClassE;
|
||||
|
||||
// We want to output to the instruction fetch if the PC fetched was wrong. If by chance the predictor was wrong about
|
||||
// the direction or class, but correct about the target we don't have the flush the pipeline. However we still
|
||||
// need this information to verify the accuracy of the predictors.
|
||||
assign BPPredWrongE = (PredictionPCWrongE & |InstrClassE) | BPPredClassNonCFIWrongE;
|
||||
|
||||
// If we have a jump, jump register or jal or jalr and the PC is wrong we need to increment the performance counter.
|
||||
assign BTBPredPCWrongE = (InstrClassE[3] | InstrClassE[1]) & PredictionPCWrongE;
|
||||
// similar with RAS
|
||||
assign RASPredPCWrongE = InstrClassE[2] & PredictionPCWrongE;
|
||||
// Finally if the real instruction class is non CFI but the predictor said it was we need to count.
|
||||
assign BPPredClassNonCFIWrongE = PredictionInstrClassWrongE & ~|InstrClassE;
|
||||
|
||||
// branch class prediction wrong.
|
||||
assign WrongPredInstrClassD = PredInstrClassD ^ InstrClassD;
|
||||
|
||||
|
||||
// Selects the BP or PC+2/4.
|
||||
mux2 #(`XLEN) pcmux0(PCPlus2or4F, BPPredPCF, SelBPPredF, PCNext0F);
|
||||
// If the prediction is wrong select the correct address.
|
||||
mux2 #(`XLEN) pcmux1(PCNext0F, PCCorrectE, BPPredWrongE, PCNext1F);
|
||||
// Correct branch/jump target.
|
||||
mux2 #(`XLEN) pccorrectemux(PCLinkE, IEUAdrE, PCSrcE, PCCorrectE);
|
||||
|
||||
// If the fence/csrw was predicted as a taken branch then we select PCF, rather PCE.
|
||||
// Effectively this is PCM+4 or the non-existant PCLinkM
|
||||
// if(`BPCLASS) begin
|
||||
mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPPredWrongM, NextValidPCE);
|
||||
// end else begin
|
||||
// assign NextValidPCE = PCE;
|
||||
// end
|
||||
|
||||
endmodule
|
||||
96
pipelined/src/ifu/bpred/RAsPredictor.sv
Normal file
96
pipelined/src/ifu/bpred/RAsPredictor.sv
Normal file
@ -0,0 +1,96 @@
|
||||
///////////////////////////////////////////
|
||||
// RASPredictor.sv
|
||||
//
|
||||
// Written: Ross Thomposn ross1728@gmail.com
|
||||
// Created: 15 February 2021
|
||||
// Modified: 25 January 2023
|
||||
//
|
||||
// Purpose: 2 bit saturating counter predictor with parameterized table depth.
|
||||
//
|
||||
// Documentation: RISC-V System on Chip Design Chapter 10 (Figure ***)
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module RASPredictor #(parameter int StackSize = 16 )(
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM, FlushD, FlushE, FlushM,
|
||||
input logic [3:0] WrongPredInstrClassD, // Prediction class is wrong
|
||||
input logic [3:0] InstrClassD, InstrClassE, PredInstrClassF, // Instr class
|
||||
input logic [`XLEN-1:0] PCLinkE, // PC of instruction after a jal
|
||||
output logic [`XLEN-1:0] RASPCF // Top of the stack
|
||||
);
|
||||
|
||||
logic CounterEn;
|
||||
localparam Depth = $clog2(StackSize);
|
||||
|
||||
logic [Depth-1:0] PtrD, PtrQ, PtrP1, PtrM1;
|
||||
logic [StackSize-1:0] [`XLEN-1:0] memory;
|
||||
integer index;
|
||||
|
||||
logic PopF;
|
||||
logic PushE;
|
||||
logic RepairD;
|
||||
logic IncrRepairD, DecRepairD;
|
||||
|
||||
logic DecrementPtr;
|
||||
|
||||
assign PopF = PredInstrClassF[2] & ~StallD & ~FlushD;
|
||||
|
||||
assign RepairD = ((WrongPredInstrClassD[2]) & ~StallE & ~FlushE) | // Wrong class undo increment or decrement.
|
||||
(~StallE & FlushE & InstrClassD[2]) | // ret in decode flushed
|
||||
(~StallM & FlushM & InstrClassE[2]) ; // ret in execution flushed
|
||||
|
||||
assign IncrRepairD = (~StallE & FlushE & InstrClassD[2]) | // ret in decode flushed
|
||||
(~StallM & FlushM & InstrClassE[2]) | // ret in execution flushed
|
||||
(WrongPredInstrClassD[2] & ~InstrClassD[2] & ~StallE & ~FlushE); // Guessed it was a ret, but its not
|
||||
|
||||
assign DecRepairD = (WrongPredInstrClassD[2] & InstrClassD[2] & ~StallE & ~FlushE); // Guessed non ret but is a ret.
|
||||
|
||||
assign PushE = InstrClassE[3] & ~StallM & ~FlushM;
|
||||
|
||||
assign CounterEn = PopF | PushE | RepairD;
|
||||
|
||||
assign DecrementPtr = (PopF | DecRepairD) & ~IncrRepairD;
|
||||
mux2 #(Depth) PtrMux(PtrP1, PtrM1, DecrementPtr, PtrD);
|
||||
|
||||
assign PtrM1 = PtrQ - 1'b1;
|
||||
assign PtrP1 = PtrQ + 1'b1;
|
||||
|
||||
flopenr #(Depth) PTR(clk, reset, CounterEn, PtrD, PtrQ);
|
||||
|
||||
// RAS must be reset.
|
||||
always_ff @ (posedge clk) begin
|
||||
if(reset) begin
|
||||
for(index=0; index<StackSize; index++)
|
||||
memory[index] <= {`XLEN{1'b0}};
|
||||
end else if(PushE) begin
|
||||
memory[PtrP1] <= #1 PCLinkE;
|
||||
end
|
||||
end
|
||||
|
||||
assign RASPCF = memory[PtrQ];
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
|
||||
|
||||
290
pipelined/src/ifu/bpred/bpred.sv
Normal file
290
pipelined/src/ifu/bpred/bpred.sv
Normal file
@ -0,0 +1,290 @@
|
||||
///////////////////////////////////////////
|
||||
// bpred.sv
|
||||
//
|
||||
// Written: Ross Thomposn ross1728@gmail.com
|
||||
// Created: 12 February 2021
|
||||
// Modified: 19 January 2023
|
||||
//
|
||||
// Purpose: Branch direction prediction and jump/branch target prediction.
|
||||
// Prediction made during the fetch stage and corrected in the execution stage.
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
`define INSTR_CLASS_PRED 1
|
||||
|
||||
module bpred (
|
||||
input logic clk, reset,
|
||||
input logic StallF, StallD, StallE, StallM, StallW,
|
||||
input logic FlushD, FlushE, FlushM, FlushW,
|
||||
// Fetch stage
|
||||
// the prediction
|
||||
input logic [31:0] InstrD, // Decompressed decode stage instruction. Used to decode instruction class
|
||||
input logic [`XLEN-1:0] PCNextF, // Next Fetch Address
|
||||
input logic [`XLEN-1:0] PCPlus2or4F, // PCF+2/4
|
||||
output logic [`XLEN-1:0] PCNext1F, // Branch Predictor predicted or corrected fetch address on miss prediction
|
||||
output logic [`XLEN-1:0] NextValidPCE, // Address of next valid instruction after the instruction in the Memory stage
|
||||
|
||||
// Update Predictor
|
||||
input logic [`XLEN-1:0] PCF, // Fetch stage instruction address
|
||||
input logic [`XLEN-1:0] PCD, // Decode stage instruction address. Also the address the branch predictor took
|
||||
input logic [`XLEN-1:0] PCE, // Execution stage instruction address
|
||||
input logic [`XLEN-1:0] PCM, // Memory stage instruction address
|
||||
|
||||
input logic [31:0] PostSpillInstrRawF, // Instruction
|
||||
|
||||
// Branch and jump outcome
|
||||
input logic PCSrcE, // Executation stage branch is taken
|
||||
input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address
|
||||
input logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address)
|
||||
output logic [3:0] InstrClassM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
|
||||
output logic JumpOrTakenBranchM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
|
||||
|
||||
// Report branch prediction status
|
||||
output logic BPPredWrongE, // Prediction is wrong
|
||||
output logic BPPredWrongM, // Prediction is wrong
|
||||
output logic DirPredictionWrongM, // Prediction direction is wrong
|
||||
output logic BTBPredPCWrongM, // Prediction target wrong
|
||||
output logic RASPredPCWrongM, // RAS prediction is wrong
|
||||
output logic PredictionInstrClassWrongM // Class prediction is wrong
|
||||
);
|
||||
|
||||
logic PredValidF;
|
||||
logic [1:0] DirPredictionF;
|
||||
|
||||
logic [3:0] BTBPredInstrClassF, PredInstrClassF, PredInstrClassD, PredInstrClassE;
|
||||
logic [`XLEN-1:0] PredPCF, RASPCF;
|
||||
logic TargetWrongE;
|
||||
logic FallThroughWrongE;
|
||||
logic PredictionPCWrongE;
|
||||
logic PredictionInstrClassWrongE;
|
||||
logic [3:0] InstrClassF, InstrClassD, InstrClassE, InstrClassW;
|
||||
logic DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE, BPPredClassNonCFIWrongE;
|
||||
|
||||
logic SelBPPredF;
|
||||
logic [`XLEN-1:0] BPPredPCF;
|
||||
logic [`XLEN-1:0] PCNext0F;
|
||||
logic [`XLEN-1:0] PCCorrectE;
|
||||
logic [3:0] WrongPredInstrClassD;
|
||||
|
||||
|
||||
logic BTBTargetWrongE;
|
||||
logic RASTargetWrongE;
|
||||
logic JumpOrTakenBranchE;
|
||||
|
||||
logic [`XLEN-1:0] PredPCD, PredPCE, RASPCD, RASPCE;
|
||||
|
||||
// Part 1 branch direction prediction
|
||||
// look into the 2 port Sram model. something is wrong.
|
||||
if (`BPRED_TYPE == "BPTWOBIT") begin:Predictor
|
||||
twoBitPredictor #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
|
||||
.PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
|
||||
.BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
|
||||
|
||||
end else if (`BPRED_TYPE == "BPGLOBAL") begin:Predictor
|
||||
globalhistory #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
|
||||
.PCNextF, .PCM, .DirPredictionF, .DirPredictionWrongE,
|
||||
.BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
|
||||
|
||||
end else if (`BPRED_TYPE == "BPSPECULATIVEGLOBAL") begin:Predictor
|
||||
speculativeglobalhistory #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
|
||||
.DirPredictionF, .DirPredictionWrongE,
|
||||
.BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]),
|
||||
.BranchInstrW(InstrClassW[0]), .WrongPredInstrClassD, .PCSrcE);
|
||||
|
||||
end else if (`BPRED_TYPE == "BPGSHARE") begin:Predictor
|
||||
gshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
|
||||
.PCNextF, .PCE, .DirPredictionF, .DirPredictionWrongE,
|
||||
.BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]), .PCSrcE);
|
||||
|
||||
end else if (`BPRED_TYPE == "BPSPECULATIVEGSHARE") begin:Predictor
|
||||
speculativegshare #(`BPRED_SIZE) DirPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
|
||||
.PCNextF, .PCF, .PCD, .PCE, .PCM, .DirPredictionF, .DirPredictionWrongE,
|
||||
.BranchInstrF(PredInstrClassF[0]), .BranchInstrD(InstrClassD[0]), .BranchInstrE(InstrClassE[0]), .BranchInstrM(InstrClassM[0]),
|
||||
.BranchInstrW(InstrClassW[0]), .WrongPredInstrClassD, .PCSrcE);
|
||||
|
||||
end else if (`BPRED_TYPE == "BPLOCALPAg") begin:Predictor
|
||||
// *** Fix me
|
||||
/* -----\/----- EXCLUDED -----\/-----
|
||||
localHistoryPredictor DirPredictor(.clk,
|
||||
.reset, .StallF, .StallE,
|
||||
.LookUpPC(PCNextF),
|
||||
.Prediction(DirPredictionF),
|
||||
// update
|
||||
.UpdatePC(PCE),
|
||||
.UpdateEN(InstrClassE[0] & ~StallE),
|
||||
.PCSrcE,
|
||||
.UpdatePrediction(InstrClassE[0]));
|
||||
-----/\----- EXCLUDED -----/\----- */
|
||||
end
|
||||
|
||||
// this predictor will have two pieces of data,
|
||||
// 1) A direction (1 = Taken, 0 = Not Taken)
|
||||
// 2) Any information which is necessary for the predictor to build its next state.
|
||||
// For a 2 bit table this is the prediction count.
|
||||
|
||||
// Part 2 Branch target address prediction
|
||||
// *** For now the BTB will house the direct and indirect targets
|
||||
|
||||
btb TargetPredictor(.clk, .reset, .StallF, .StallD, .StallM, .FlushD, .FlushM,
|
||||
.PCNextF, .PCF, .PCD, .PCE,
|
||||
.PredPCF,
|
||||
.BTBPredInstrClassF,
|
||||
.PredValidF,
|
||||
.PredictionInstrClassWrongE,
|
||||
.IEUAdrE,
|
||||
.InstrClassE);
|
||||
|
||||
// Part 3 RAS
|
||||
// *** need to add the logic to restore RAS on flushes. We will use incr for this.
|
||||
// *** needs to include flushX
|
||||
RASPredictor RASPredictor(.clk, .reset, .StallF, .StallD, .StallE, .StallM, .FlushD, .FlushE, .FlushM,
|
||||
.PredInstrClassF, .InstrClassD, .InstrClassE,
|
||||
.WrongPredInstrClassD, .RASPCF, .PCLinkE);
|
||||
|
||||
assign BPPredPCF = PredInstrClassF[2] ? RASPCF : PredPCF;
|
||||
|
||||
// the branch predictor needs a compact decoding of the instruction class.
|
||||
if (`INSTR_CLASS_PRED == 0) begin : DirectClassDecode
|
||||
logic [4:0] CompressedOpcF;
|
||||
logic [3:0] InstrClassF;
|
||||
logic cjal, cj, cjr, cjalr;
|
||||
|
||||
assign CompressedOpcF = {PostSpillInstrRawF[1:0], PostSpillInstrRawF[15:13]};
|
||||
|
||||
assign cjal = CompressedOpcF == 5'h09 & `XLEN == 32;
|
||||
assign cj = CompressedOpcF == 5'h0d;
|
||||
assign cjr = CompressedOpcF == 5'h14 & ~PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0;
|
||||
assign cjalr = CompressedOpcF == 5'h14 & PostSpillInstrRawF[12] & PostSpillInstrRawF[6:2] == 5'b0 & PostSpillInstrRawF[11:7] != 5'b0;
|
||||
|
||||
assign InstrClassF[0] = PostSpillInstrRawF[6:0] == 7'h63 |
|
||||
(`C_SUPPORTED & CompressedOpcF[4:1] == 4'h7);
|
||||
|
||||
assign InstrClassF[1] = (PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) != 5'h01 & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump register, but not return
|
||||
(PostSpillInstrRawF[6:0] == 7'h6F & (PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01) | // jump, RD != x1 or x5
|
||||
(`C_SUPPORTED & (cj | (cjr & ((PostSpillInstrRawF[11:7] & 5'h1B) != 5'h01)) ));
|
||||
|
||||
assign InstrClassF[2] = PostSpillInstrRawF[6:0] == 7'h67 & (PostSpillInstrRawF[19:15] & 5'h1B) == 5'h01 | // return must return to ra or r5
|
||||
(`C_SUPPORTED & (cjalr | cjr) & ((PostSpillInstrRawF[11:7] & 5'h1B) == 5'h01));
|
||||
|
||||
assign InstrClassF[3] = ((PostSpillInstrRawF[6:0] & 7'h77) == 7'h67 & (PostSpillInstrRawF[11:07] & 5'h1B) == 5'h01) | // jal(r) must link to ra or x5
|
||||
(`C_SUPPORTED & (cjal | (cjalr & (PostSpillInstrRawF[11:7] & 5'h1b) == 5'h01)));
|
||||
assign PredInstrClassF = InstrClassF;
|
||||
assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1]) |
|
||||
PredInstrClassF[2] |
|
||||
(PredInstrClassF[1]) ;
|
||||
end else begin
|
||||
assign PredInstrClassF = BTBPredInstrClassF;
|
||||
assign SelBPPredF = (PredInstrClassF[0] & DirPredictionF[1] & PredValidF) |
|
||||
PredInstrClassF[2] |
|
||||
(PredInstrClassF[1] & PredValidF) ;
|
||||
end
|
||||
|
||||
|
||||
assign InstrClassD[3] = (InstrD[6:0] & 7'h77) == 7'h67 & (InstrD[11:07] & 5'h1B) == 5'h01; // jal(r) must link to ra or x5
|
||||
assign InstrClassD[2] = InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) == 5'h01; // return must return to ra or r5
|
||||
assign InstrClassD[1] = (InstrD[6:0] == 7'h67 & (InstrD[19:15] & 5'h1B) != 5'h01 & (InstrD[11:7] & 5'h1B) != 5'h01) | // jump register, but not return
|
||||
(InstrD[6:0] == 7'h6F & (InstrD[11:7] & 5'h1B) != 5'h01); // jump, RD != x1 or x5
|
||||
assign InstrClassD[0] = InstrD[6:0] == 7'h63; // branch
|
||||
flopenrc #(4) InstrClassRegE(clk, reset, FlushE, ~StallE, InstrClassD, InstrClassE);
|
||||
flopenrc #(4) InstrClassRegM(clk, reset, FlushM, ~StallM, InstrClassE, InstrClassM);
|
||||
flopenrc #(4) InstrClassRegW(clk, reset, FlushW, ~StallW, InstrClassM, InstrClassW);
|
||||
flopenrc #(1) BPPredWrongMReg(clk, reset, FlushM, ~StallM, BPPredWrongE, BPPredWrongM);
|
||||
flopenrc #(1) JumpOrTakenBranchMReg(clk, reset, FlushM, ~StallM, JumpOrTakenBranchE, JumpOrTakenBranchM);
|
||||
|
||||
// branch predictor
|
||||
flopenrc #(4) BPPredWrongRegM(clk, reset, FlushM, ~StallM,
|
||||
{DirPredictionWrongE, BTBPredPCWrongE, RASPredPCWrongE, PredictionInstrClassWrongE},
|
||||
{DirPredictionWrongM, BTBPredPCWrongM, RASPredPCWrongM, PredictionInstrClassWrongM});
|
||||
|
||||
// pipeline the class
|
||||
flopenrc #(4) PredInstrClassRegD(clk, reset, FlushD, ~StallD, PredInstrClassF, PredInstrClassD);
|
||||
flopenrc #(4) PredInstrClassRegE(clk, reset, FlushE, ~StallE, PredInstrClassD, PredInstrClassE);
|
||||
|
||||
// Check the prediction
|
||||
// first check if the target or fallthrough address matches what was predicted.
|
||||
assign TargetWrongE = IEUAdrE != PCD;
|
||||
assign FallThroughWrongE = PCLinkE != PCD;
|
||||
// If the target is taken check the target rather than fallthrough. The instruction needs to be a branch if PCSrcE is selected
|
||||
// Remember the bpred can incorrectly predict a non cfi instruction as a branch taken. If the real instruction is non cfi
|
||||
// it must have selected the fall through.
|
||||
assign PredictionPCWrongE = (PCSrcE & (|InstrClassE) ? TargetWrongE : FallThroughWrongE);
|
||||
|
||||
// The branch direction also need to checked.
|
||||
// However if the direction is wrong then the pc will be wrong. This is only relavent to checking the
|
||||
// accuracy of the direciton prediction.
|
||||
//assign DirPredictionWrongE = (BPPredE[1] ^ PCSrcE) & InstrClassE[0];
|
||||
|
||||
// Finally we need to check if the class is wrong. When the class is wrong the BTB needs to be updated.
|
||||
// Also we want to track this in a performance counter.
|
||||
assign PredictionInstrClassWrongE = InstrClassE != PredInstrClassE;
|
||||
|
||||
// We want to output to the instruction fetch if the PC fetched was wrong. If by chance the predictor was wrong about
|
||||
// the direction or class, but correct about the target we don't have the flush the pipeline. However we still
|
||||
// need this information to verify the accuracy of the predictors.
|
||||
assign BPPredWrongE = (PredictionPCWrongE & |InstrClassE) | BPPredClassNonCFIWrongE;
|
||||
|
||||
// If we have a jump, jump register or jal or jalr and the PC is wrong we need to increment the performance counter.
|
||||
//assign BTBPredPCWrongE = (InstrClassE[3] | InstrClassE[1] | InstrClassE[0]) & PredictionPCWrongE;
|
||||
//assign BTBPredPCWrongE = TargetWrongE & (InstrClassE[3] | InstrClassE[1] | InstrClassE[0]) & PCSrcE;
|
||||
assign BTBPredPCWrongE = BTBTargetWrongE;
|
||||
|
||||
// similar with RAS. Over counts ras if the class prediction was wrong.
|
||||
//assign RASPredPCWrongE = TargetWrongE & InstrClassE[2] & PCSrcE;
|
||||
assign RASPredPCWrongE = RASTargetWrongE;
|
||||
// Finally if the real instruction class is non CFI but the predictor said it was we need to count.
|
||||
assign BPPredClassNonCFIWrongE = PredictionInstrClassWrongE & ~|InstrClassE;
|
||||
|
||||
// branch class prediction wrong.
|
||||
assign WrongPredInstrClassD = PredInstrClassD ^ InstrClassD;
|
||||
|
||||
// Selects the BP or PC+2/4.
|
||||
mux2 #(`XLEN) pcmux0(PCPlus2or4F, BPPredPCF, SelBPPredF, PCNext0F);
|
||||
// If the prediction is wrong select the correct address.
|
||||
mux2 #(`XLEN) pcmux1(PCNext0F, PCCorrectE, BPPredWrongE, PCNext1F);
|
||||
// Correct branch/jump target.
|
||||
mux2 #(`XLEN) pccorrectemux(PCLinkE, IEUAdrE, PCSrcE, PCCorrectE);
|
||||
|
||||
// If the fence/csrw was predicted as a taken branch then we select PCF, rather PCE.
|
||||
// Effectively this is PCM+4 or the non-existant PCLinkM
|
||||
// if(`BPCLASS) begin
|
||||
mux2 #(`XLEN) pcmuxBPWrongInvalidateFlush(PCE, PCF, BPPredWrongM, NextValidPCE);
|
||||
// end else begin
|
||||
// assign NextValidPCE = PCE;
|
||||
// end
|
||||
|
||||
// performance counters
|
||||
// 1. class (class wrong / minstret) (PredictionInstrClassWrongM / csr) // Correct now
|
||||
// 2. target btb (btb target wrong / class[0,1,3]) (btb target wrong / (br + j + jal)
|
||||
// 3. target ras (ras target wrong / class[2])
|
||||
// 4. direction (br dir wrong / class[0])
|
||||
|
||||
assign BTBTargetWrongE = (PredPCE != IEUAdrE) & (InstrClassE[0] | InstrClassE[1] | InstrClassE[3]) & PCSrcE;
|
||||
assign RASTargetWrongE = (RASPCE != IEUAdrE) & InstrClassE[2] & PCSrcE;
|
||||
|
||||
assign JumpOrTakenBranchE = (InstrClassE[0] & PCSrcE) | InstrClassE[1] | InstrClassE[3];
|
||||
|
||||
flopenrc #(`XLEN) BTBTargetDReg(clk, reset, FlushD, ~StallD, PredPCF, PredPCD);
|
||||
flopenrc #(`XLEN) BTBTargetEReg(clk, reset, FlushE, ~StallE, PredPCD, PredPCE);
|
||||
|
||||
flopenrc #(`XLEN) RASTargetDReg(clk, reset, FlushD, ~StallD, RASPCF, RASPCD);
|
||||
flopenrc #(`XLEN) RASTargetEReg(clk, reset, FlushE, ~StallE, RASPCD, RASPCE);
|
||||
|
||||
endmodule
|
||||
109
pipelined/src/ifu/bpred/btb.sv
Normal file
109
pipelined/src/ifu/bpred/btb.sv
Normal file
@ -0,0 +1,109 @@
|
||||
///////////////////////////////////////////
|
||||
// btb.sv
|
||||
//
|
||||
// Written: Ross Thomposn ross1728@gmail.com
|
||||
// Created: February 15, 2021
|
||||
// Modified: 24 January 2023
|
||||
//
|
||||
// Purpose: Branch Target Buffer (BTB). The BTB predicts the target address of all control flow instructions.
|
||||
// It also guesses the type of instrution; jalr(r), return, jump (jr), or branch.
|
||||
//
|
||||
// Documentation: RISC-V System on Chip Design Chapter 10 (Figure ***)
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module btb #(parameter int Depth = 10 ) (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallM, FlushD, FlushM,
|
||||
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, // PC at various stages
|
||||
output logic [`XLEN-1:0] PredPCF, // BTB's guess at PC
|
||||
output logic [3:0] BTBPredInstrClassF, // BTB's guess at instruction class
|
||||
output logic PredValidF, // BTB's guess is valid
|
||||
// update
|
||||
input logic PredictionInstrClassWrongE, // BTB's instruction class guess was wrong
|
||||
input logic [`XLEN-1:0] IEUAdrE, // Branch/jump target address to insert into btb
|
||||
input logic [3:0] InstrClassE // Instruction class to insert into btb
|
||||
);
|
||||
|
||||
localparam TotalDepth = 2 ** Depth;
|
||||
logic [TotalDepth-1:0] ValidBits;
|
||||
logic [Depth-1:0] PCNextFIndex, PCFIndex, PCDIndex, PCEIndex;
|
||||
logic [`XLEN-1:0] ResetPC;
|
||||
logic MatchF, MatchD, MatchE, MatchNextX, MatchXF;
|
||||
logic [`XLEN+3:0] ForwardBTBPrediction, ForwardBTBPredictionF;
|
||||
logic [`XLEN+3:0] TableBTBPredictionF;
|
||||
logic [`XLEN-1:0] PredPCD;
|
||||
logic [3:0] PredInstrClassD; // *** copy of reg outside module
|
||||
logic UpdateEn;
|
||||
logic TablePredValidF;
|
||||
|
||||
// hashing function for indexing the PC
|
||||
// We have Depth bits to index, but XLEN bits as the input.
|
||||
// bit 0 is always 0, bit 1 is 0 if using 4 byte instructions, but is not always 0 if
|
||||
// using compressed instructions. XOR bit 1 with the MSB of index.
|
||||
assign PCFIndex = {PCF[Depth+1] ^ PCF[1], PCF[Depth:2]};
|
||||
assign PCDIndex = {PCD[Depth+1] ^ PCD[1], PCD[Depth:2]};
|
||||
assign PCEIndex = {PCE[Depth+1] ^ PCE[1], PCE[Depth:2]};
|
||||
|
||||
// must output a valid PC and valid bit during reset. Because only PCF, not PCNextF is reset, PCNextF is invalid
|
||||
// during reset. The BTB must produce a non X PC1NextF to allow the simulation to run.
|
||||
// While thie mux could be included in IFU it is not necessary for the IROM/I$/bus.
|
||||
// For now it is optimal to leave it here.
|
||||
assign ResetPC = `RESET_VECTOR;
|
||||
assign PCNextFIndex = reset ? ResetPC[Depth+1:2] : {PCNextF[Depth+1] ^ PCNextF[1], PCNextF[Depth:2]};
|
||||
|
||||
assign MatchF = PCNextFIndex == PCFIndex;
|
||||
assign MatchD = PCNextFIndex == PCDIndex;
|
||||
assign MatchE = PCNextFIndex == PCEIndex;
|
||||
assign MatchNextX = MatchF | MatchD | MatchE;
|
||||
|
||||
flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
|
||||
|
||||
assign ForwardBTBPrediction = MatchF ? {BTBPredInstrClassF, PredPCF} :
|
||||
MatchD ? {PredInstrClassD, PredPCD} :
|
||||
{InstrClassE, IEUAdrE} ;
|
||||
|
||||
flopenr #(`XLEN+4) ForwardBTBPredicitonReg(clk, reset, ~StallF, ForwardBTBPrediction, ForwardBTBPredictionF);
|
||||
|
||||
assign {BTBPredInstrClassF, PredPCF} = MatchXF ? ForwardBTBPredictionF : TableBTBPredictionF;
|
||||
|
||||
always_ff @ (posedge clk) begin
|
||||
if (reset) begin
|
||||
ValidBits <= #1 {TotalDepth{1'b0}};
|
||||
end else if ((UpdateEn) & ~StallM & ~FlushM) begin
|
||||
ValidBits[PCEIndex] <= #1 |InstrClassE;
|
||||
end
|
||||
if(~StallF | reset) TablePredValidF = ValidBits[PCNextFIndex];
|
||||
end
|
||||
|
||||
assign PredValidF = MatchXF ? 1'b1 : TablePredValidF;
|
||||
|
||||
assign UpdateEn = |InstrClassE | PredictionInstrClassWrongE;
|
||||
|
||||
// An optimization may be using a PC relative address.
|
||||
ram2p1r1wbe #(2**Depth, `XLEN+4) memory(
|
||||
.clk, .ce1(~StallF | reset), .ra1(PCNextFIndex), .rd1(TableBTBPredictionF),
|
||||
.ce2(~StallM & ~FlushM), .wa2(PCEIndex), .wd2({InstrClassE, IEUAdrE}), .we2(UpdateEn), .bwe2('1));
|
||||
|
||||
flopenrc #(`XLEN+4) BTBD(clk, reset, FlushD, ~StallD, {BTBPredInstrClassF, PredPCF}, {PredInstrClassD, PredPCD});
|
||||
|
||||
endmodule
|
||||
@ -28,22 +28,19 @@
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module foldedgshare
|
||||
#(parameter int k = 16,
|
||||
parameter int depth = 10
|
||||
)
|
||||
(input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM, StallW,
|
||||
input logic FlushD, FlushE, FlushM, FlushW,
|
||||
module foldedgshare #(parameter k = 16, depth = 10) (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM, StallW,
|
||||
input logic FlushD, FlushE, FlushM, FlushW,
|
||||
// input logic [`XLEN-1:0] LookUpPC,
|
||||
output logic [1:0] DirPredictionF,
|
||||
output logic DirPredictionWrongE,
|
||||
// update
|
||||
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
|
||||
input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
|
||||
input logic PCSrcE
|
||||
);
|
||||
output logic [1:0] DirPredictionF,
|
||||
output logic DirPredictionWrongE,
|
||||
// update
|
||||
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
|
||||
input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
|
||||
input logic PCSrcE
|
||||
);
|
||||
|
||||
logic MatchF, MatchD, MatchE, MatchM, MatchW;
|
||||
logic MatchNextX, MatchXF;
|
||||
@ -57,13 +54,13 @@ module foldedgshare
|
||||
logic [k:0] GHRNextD, GHRNextE, GHRNextM, GHRNextW;
|
||||
logic [k-1:0] IndexNextF, IndexF;
|
||||
logic [k-1:0] IndexD, IndexE, IndexM, IndexW;
|
||||
logic [depth-1:0] FinalIndexNextF, FinalIndexW;
|
||||
logic [depth-1:0] FinalIndexNextF, FinalIndexW;
|
||||
|
||||
logic PCSrcM, PCSrcW;
|
||||
logic [`XLEN-1:0] PCW;
|
||||
|
||||
logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF;
|
||||
localparam int delta = 2 * depth - k;
|
||||
localparam delta = 2 * depth - k;
|
||||
|
||||
assign IndexNextF = GHRNextF ^ {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
|
||||
assign IndexF = GHRF ^ {PCF[k+1] ^ PCF[1], PCF[k:2]};
|
||||
@ -77,7 +74,7 @@ module foldedgshare
|
||||
assign FinalIndexNextF = IndexNextF[depth-1:0] ^ {{delta{1'b0}} , IndexNextF[k-1:depth]};
|
||||
assign FinalIndexW = IndexW[depth-1:0] ^ {{delta{1'b0}} , IndexW[k-1:depth]};
|
||||
|
||||
ram2p1r1wbefix #(2**depth, 2) PHT(.clk(clk),
|
||||
ram2p1r1wbe #(2**depth, 2) PHT(.clk(clk),
|
||||
.ce1(~StallF | reset), .ce2(~StallW & ~FlushW),
|
||||
.ra1(FinalIndexNextF),
|
||||
.rd1(TableDirPredictionF),
|
||||
@ -28,36 +28,34 @@
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module globalhistory
|
||||
#(parameter int k = 10
|
||||
)
|
||||
(input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM,
|
||||
input logic FlushD, FlushE, FlushM,
|
||||
// input logic [`XLEN-1:0] LookUpPC,
|
||||
output logic [1:0] DirPredictionF,
|
||||
output logic DirPredictionWrongE,
|
||||
// update
|
||||
input logic [`XLEN-1:0] PCNextF, PCM,
|
||||
input logic BranchInstrE, BranchInstrM, PCSrcE
|
||||
);
|
||||
module globalhistory #(parameter k = 10) (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM,
|
||||
input logic FlushD, FlushE, FlushM,
|
||||
// input logic [`XLEN-1:0] LookUpPC,
|
||||
output logic [1:0] DirPredictionF,
|
||||
output logic DirPredictionWrongE,
|
||||
// update
|
||||
input logic [`XLEN-1:0] PCNextF, PCM,
|
||||
input logic BranchInstrE, BranchInstrM, PCSrcE
|
||||
);
|
||||
|
||||
logic [1:0] DirPredictionD, DirPredictionE;
|
||||
logic [1:0] NewDirPredictionE, NewDirPredictionM;
|
||||
|
||||
logic [k-1:0] GHRF, GHRD, GHRE, GHRM, GHR;
|
||||
logic [k-1:0] GHRF, GHRD, GHRE, GHR;
|
||||
logic [k-1:0] GHRNext;
|
||||
logic PCSrcM;
|
||||
|
||||
|
||||
ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk),
|
||||
ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
|
||||
.ce1(~StallF), .ce2(~StallM & ~FlushM),
|
||||
.ra1(GHR),
|
||||
.rd1(DirPredictionF),
|
||||
.wa2(GHRM),
|
||||
.wd2(NewDirPredictionM),
|
||||
.we2(BranchInstrM & ~StallM & ~FlushM),
|
||||
.wa2(GHRE),
|
||||
.wd2(NewDirPredictionE),
|
||||
.we2(BranchInstrE & ~StallM & ~FlushM),
|
||||
.bwe2(1'b1));
|
||||
|
||||
flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD);
|
||||
@ -76,7 +74,6 @@ module globalhistory
|
||||
flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF);
|
||||
flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD);
|
||||
flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE);
|
||||
flopenrc #(k) GHRMReg(clk, reset, FlushM, ~StallM, GHRE, GHRM);
|
||||
|
||||
|
||||
endmodule
|
||||
@ -28,39 +28,36 @@
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module gshare
|
||||
#(parameter int k = 10
|
||||
)
|
||||
(input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM,
|
||||
input logic FlushD, FlushE, FlushM,
|
||||
// input logic [`XLEN-1:0] LookUpPC,
|
||||
output logic [1:0] DirPredictionF,
|
||||
output logic DirPredictionWrongE,
|
||||
// update
|
||||
input logic [`XLEN-1:0] PCNextF, PCM,
|
||||
input logic BranchInstrE, BranchInstrM, PCSrcE
|
||||
);
|
||||
module gshare #(parameter k = 10) (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM,
|
||||
input logic FlushD, FlushE, FlushM,
|
||||
output logic [1:0] DirPredictionF,
|
||||
output logic DirPredictionWrongE,
|
||||
// update
|
||||
input logic [`XLEN-1:0] PCNextF, PCE,
|
||||
input logic BranchInstrE, BranchInstrM, PCSrcE
|
||||
);
|
||||
|
||||
logic [k-1:0] IndexNextF, IndexM;
|
||||
logic [k-1:0] IndexNextF, IndexE;
|
||||
logic [1:0] DirPredictionD, DirPredictionE;
|
||||
logic [1:0] NewDirPredictionE, NewDirPredictionM;
|
||||
|
||||
logic [k-1:0] GHRF, GHRD, GHRE, GHRM, GHR;
|
||||
logic [k-1:0] GHRF, GHRD, GHRE, GHR;
|
||||
logic [k-1:0] GHRNext;
|
||||
logic PCSrcM;
|
||||
|
||||
assign IndexNextF = GHR & {PCNextF[k+1] ^ PCNextF[1], PCNextF[k:2]};
|
||||
assign IndexM = GHRM & {PCM[k+1] ^ PCM[1], PCM[k:2]};
|
||||
assign IndexE = GHRE & {PCE[k+1] ^ PCE[1], PCE[k:2]};
|
||||
|
||||
ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk),
|
||||
ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
|
||||
.ce1(~StallF), .ce2(~StallM & ~FlushM),
|
||||
.ra1(IndexNextF),
|
||||
.rd1(DirPredictionF),
|
||||
.wa2(IndexM),
|
||||
.wd2(NewDirPredictionM),
|
||||
.we2(BranchInstrM & ~StallM & ~FlushM),
|
||||
.wa2(IndexE),
|
||||
.wd2(NewDirPredictionE),
|
||||
.we2(BranchInstrE & ~StallM & ~FlushM),
|
||||
.bwe2(1'b1));
|
||||
|
||||
flopenrc #(2) PredictionRegD(clk, reset, FlushD, ~StallD, DirPredictionF, DirPredictionD);
|
||||
@ -78,7 +75,6 @@ module gshare
|
||||
flopenrc #(k) GHRFReg(clk, reset, FlushD, ~StallF, GHR, GHRF);
|
||||
flopenrc #(k) GHRDReg(clk, reset, FlushD, ~StallD, GHRF, GHRD);
|
||||
flopenrc #(k) GHREReg(clk, reset, FlushE, ~StallE, GHRD, GHRE);
|
||||
flopenrc #(k) GHRMReg(clk, reset, FlushM, ~StallM, GHRE, GHRM);
|
||||
|
||||
|
||||
endmodule
|
||||
@ -28,23 +28,20 @@
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module localHistoryPredictor
|
||||
#( parameter int m = 6, // 2^m = number of local history branches
|
||||
parameter int k = 10 // number of past branches stored
|
||||
)
|
||||
(input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallE,
|
||||
input logic [`XLEN-1:0] LookUpPC,
|
||||
output logic [1:0] Prediction,
|
||||
// update
|
||||
input logic [`XLEN-1:0] UpdatePC,
|
||||
input logic UpdateEN, PCSrcE,
|
||||
input logic [1:0] UpdatePrediction
|
||||
|
||||
);
|
||||
module localHistoryPredictor #(parameter m = 6, // 2^m = number of local history branches
|
||||
k = 10) ( // number of past branches stored
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallE,
|
||||
input logic [`XLEN-1:0] LookUpPC,
|
||||
output logic [1:0] Prediction,
|
||||
// update
|
||||
input logic [`XLEN-1:0] UpdatePC,
|
||||
input logic UpdateEN, PCSrcE,
|
||||
input logic [1:0] UpdatePrediction
|
||||
);
|
||||
|
||||
logic [2**m-1:0] [k-1:0] LHRNextF;
|
||||
logic [2**m-1:0][k-1:0] LHRNextF;
|
||||
logic [k-1:0] LHRF, ForwardLHRNext, LHRFNext;
|
||||
logic [m-1:0] LookUpPCIndex, UpdatePCIndex;
|
||||
logic [1:0] PredictionMemory;
|
||||
@ -12,41 +12,35 @@
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// MIT LICENSE
|
||||
// Permission is hereby granted, free of charge, to any person obtaining a copy of this
|
||||
// software and associated documentation files (the "Software"), to deal in the Software
|
||||
// without restriction, including without limitation the rights to use, copy, modify, merge,
|
||||
// publish, distribute, sublicense, and/or sell copies of the Software, and to permit persons
|
||||
// to whom the Software is furnished to do so, subject to the following conditions:
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// The above copyright notice and this permission notice shall be included in all copies or
|
||||
// substantial portions of the Software.
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED,
|
||||
// INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
|
||||
// PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
|
||||
// BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
|
||||
// TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE
|
||||
// OR OTHER DEALINGS IN THE SOFTWARE.
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module optgshare
|
||||
#(parameter int k = 10
|
||||
)
|
||||
(input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM, StallW,
|
||||
input logic FlushD, FlushE, FlushM, FlushW,
|
||||
module optgshare #(parameter k = 10) (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM, StallW,
|
||||
input logic FlushD, FlushE, FlushM, FlushW,
|
||||
// input logic [`XLEN-1:0] LookUpPC,
|
||||
output logic [1:0] DirPredictionF,
|
||||
output logic DirPredictionWrongE,
|
||||
// update
|
||||
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
|
||||
input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
|
||||
input logic PCSrcE
|
||||
);
|
||||
output logic [1:0] DirPredictionF,
|
||||
output logic DirPredictionWrongE,
|
||||
// update
|
||||
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
|
||||
input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
|
||||
input logic PCSrcE
|
||||
);
|
||||
|
||||
logic MatchF, MatchD, MatchE, MatchM, MatchW;
|
||||
logic MatchNextX, MatchXF;
|
||||
@ -153,7 +147,7 @@ module optgshare
|
||||
assign IndexM = GHRM[k-1:0] ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
|
||||
assign IndexW = GHRW[k-1:0] ^ {PCW[k+1] ^ PCW[1], PCW[k:2]};
|
||||
|
||||
ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk),
|
||||
ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
|
||||
.ce1(~StallF | reset), .ce2(~StallW & ~FlushW),
|
||||
.ra1(IndexNextF),
|
||||
.rd1(TableDirPredictionF),
|
||||
142
pipelined/src/ifu/bpred/speculativeglobalhistory.sv
Normal file
142
pipelined/src/ifu/bpred/speculativeglobalhistory.sv
Normal file
@ -0,0 +1,142 @@
|
||||
///////////////////////////////////////////
|
||||
// speculativeglobalhistory.sv
|
||||
//
|
||||
// Written: Shreya Sanghai
|
||||
// Email: ssanghai@hmc.edu
|
||||
// Created: March 16, 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Global History Branch predictor with parameterized global history register
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module speculativeglobalhistory #(parameter int k = 10 ) (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM, StallW,
|
||||
input logic FlushD, FlushE, FlushM, FlushW,
|
||||
output logic [1:0] DirPredictionF,
|
||||
output logic DirPredictionWrongE,
|
||||
// update
|
||||
input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
|
||||
input logic [3:0] WrongPredInstrClassD,
|
||||
input logic PCSrcE
|
||||
);
|
||||
|
||||
logic MatchF, MatchD, MatchE;
|
||||
logic MatchNextX, MatchXF;
|
||||
|
||||
logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE;
|
||||
logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE;
|
||||
|
||||
logic [k-1:0] GHRF;
|
||||
logic GHRExtraF;
|
||||
logic [k-1:0] GHRD, GHRE, GHRM, GHRW;
|
||||
logic [k-1:0] GHRNextF;
|
||||
logic [k-1:0] GHRNextD;
|
||||
logic [k-1:0] GHRNextE, GHRNextM, GHRNextW;
|
||||
logic [k-1:0] IndexNextF, IndexF;
|
||||
logic [k-1:0] IndexD, IndexE;
|
||||
|
||||
|
||||
logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF;
|
||||
|
||||
assign IndexNextF = GHRNextF;
|
||||
assign IndexF = GHRF;
|
||||
assign IndexD = GHRD[k-1:0];
|
||||
assign IndexE = GHRE[k-1:0];
|
||||
|
||||
ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
|
||||
.ce1(~StallF | reset), .ce2(~StallM & ~FlushM),
|
||||
.ra1(IndexNextF),
|
||||
.rd1(TableDirPredictionF),
|
||||
.wa2(IndexE),
|
||||
.wd2(NewDirPredictionE),
|
||||
.we2(BranchInstrE & ~StallM & ~FlushM),
|
||||
.bwe2(1'b1));
|
||||
|
||||
// if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage
|
||||
// and then register for use in the Fetch stage.
|
||||
assign MatchF = BranchInstrF & ~FlushD & (IndexNextF == IndexF);
|
||||
assign MatchD = BranchInstrD & ~FlushE & (IndexNextF == IndexD);
|
||||
assign MatchE = BranchInstrE & ~FlushM & (IndexNextF == IndexE);
|
||||
assign MatchNextX = MatchF | MatchD | MatchE;
|
||||
|
||||
flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
|
||||
|
||||
assign ForwardNewDirPrediction = MatchF ? NewDirPredictionF :
|
||||
MatchD ? NewDirPredictionD :
|
||||
NewDirPredictionE ;
|
||||
|
||||
flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF);
|
||||
|
||||
assign DirPredictionF = MatchXF ? ForwardDirPredictionF : TableDirPredictionF;
|
||||
|
||||
// DirPrediction pipeline
|
||||
flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD);
|
||||
flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE);
|
||||
|
||||
// New prediction pipeline
|
||||
assign NewDirPredictionF = {DirPredictionF[1], DirPredictionF[1]};
|
||||
|
||||
flopenr #(2) NewPredDReg(clk, reset, ~StallD, NewDirPredictionF, NewDirPredictionD);
|
||||
satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
|
||||
|
||||
// GHR pipeline
|
||||
// this version fails the regression test do to pessimistic x propagation.
|
||||
// assign GHRNextF = FlushD | DirPredictionWrongE ? GHRNextD[k-1:0] :
|
||||
// BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} :
|
||||
// GHRF;
|
||||
|
||||
always_comb begin
|
||||
if(FlushD | DirPredictionWrongE) begin
|
||||
GHRNextF = GHRNextD[k-1:0];
|
||||
end else if(BranchInstrF) GHRNextF = {DirPredictionF[1], GHRF[k-1:1]};
|
||||
else GHRNextF = GHRF;
|
||||
end
|
||||
|
||||
flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF);
|
||||
flopenr #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRF[0], GHRExtraF);
|
||||
|
||||
// use with out instruction class prediction
|
||||
//assign GHRNextD = FlushD ? GHRNextE[k-1:0] : GHRF[k-1:0];
|
||||
// with instruction class prediction
|
||||
assign GHRNextD = (FlushD | DirPredictionWrongE) ? GHRNextE[k-1:0] :
|
||||
WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], GHRF[k-1:1]} : // shift right
|
||||
WrongPredInstrClassD[0] & ~BranchInstrD ? {GHRF[k-2:0], GHRExtraF}: // shift left
|
||||
GHRF[k-1:0];
|
||||
|
||||
flopenr #(k) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD);
|
||||
|
||||
assign GHRNextE = BranchInstrE & ~FlushM ? {PCSrcE, GHRD[k-2:0]} : // if the branch is not flushed
|
||||
FlushE ? GHRNextM : // branch is flushed
|
||||
GHRD;
|
||||
flopenr #(k) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, GHRE);
|
||||
|
||||
assign GHRNextM = FlushM ? GHRNextW : GHRE;
|
||||
flopenr #(k) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM);
|
||||
|
||||
assign GHRNextW = FlushW ? GHRW : GHRM;
|
||||
flopenr #(k) GHRWReg(clk, reset, (BranchInstrW & ~StallW) | FlushW, GHRNextW, GHRW);
|
||||
|
||||
assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
|
||||
|
||||
endmodule
|
||||
@ -28,39 +28,35 @@
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module speculativegshare
|
||||
#(parameter int k = 10
|
||||
)
|
||||
(input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM, StallW,
|
||||
input logic FlushD, FlushE, FlushM, FlushW,
|
||||
// input logic [`XLEN-1:0] LookUpPC,
|
||||
output logic [1:0] DirPredictionF,
|
||||
output logic DirPredictionWrongE,
|
||||
// update
|
||||
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
|
||||
input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
|
||||
input logic [3:0] WrongPredInstrClassD,
|
||||
input logic PCSrcE
|
||||
);
|
||||
module speculativegshare #(parameter int k = 10 ) (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM, StallW,
|
||||
input logic FlushD, FlushE, FlushM, FlushW,
|
||||
output logic [1:0] DirPredictionF,
|
||||
output logic DirPredictionWrongE,
|
||||
// update
|
||||
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
|
||||
input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
|
||||
input logic [3:0] WrongPredInstrClassD,
|
||||
input logic PCSrcE
|
||||
);
|
||||
|
||||
logic MatchF, MatchD, MatchE, MatchM;
|
||||
logic MatchF, MatchD, MatchE;
|
||||
logic MatchNextX, MatchXF;
|
||||
|
||||
logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE;
|
||||
logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE, NewDirPredictionM;
|
||||
logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE;
|
||||
|
||||
logic [k-1:0] GHRF;
|
||||
logic [k:0] GHRD, OldGHRE, GHRE, GHRM, GHRW;
|
||||
logic [k-1:0] GHRNextF;
|
||||
logic [k:-1] GHRNextD, OldGHRD;
|
||||
logic [k:0] GHRNextE, GHRNextM, GHRNextW;
|
||||
logic GHRExtraF;
|
||||
logic [k-1:0] GHRD, GHRE, GHRM, GHRW;
|
||||
logic [k-1:0] GHRNextF;
|
||||
logic [k-1:0] GHRNextD;
|
||||
logic [k-1:0] GHRNextE, GHRNextM, GHRNextW;
|
||||
logic [k-1:0] IndexNextF, IndexF;
|
||||
logic [k-1:0] IndexD, IndexE, IndexM;
|
||||
logic [k-1:0] IndexD, IndexE;
|
||||
|
||||
logic PCSrcM, PCSrcW;
|
||||
logic [`XLEN-1:0] PCW;
|
||||
|
||||
logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF;
|
||||
|
||||
@ -68,15 +64,14 @@ module speculativegshare
|
||||
assign IndexF = GHRF ^ {PCF[k+1] ^ PCF[1], PCF[k:2]};
|
||||
assign IndexD = GHRD[k-1:0] ^ {PCD[k+1] ^ PCD[1], PCD[k:2]};
|
||||
assign IndexE = GHRE[k-1:0] ^ {PCE[k+1] ^ PCE[1], PCE[k:2]};
|
||||
assign IndexM = GHRM[k-1:0] ^ {PCM[k+1] ^ PCM[1], PCM[k:2]};
|
||||
|
||||
ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk),
|
||||
.ce1(~StallF | reset), .ce2(~StallW & ~FlushW),
|
||||
ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
|
||||
.ce1(~StallF | reset), .ce2(~StallM & ~FlushM),
|
||||
.ra1(IndexNextF),
|
||||
.rd1(TableDirPredictionF),
|
||||
.wa2(IndexM),
|
||||
.wd2(NewDirPredictionM),
|
||||
.we2(BranchInstrM & ~StallW & ~FlushW),
|
||||
.wa2(IndexE),
|
||||
.wd2(NewDirPredictionE),
|
||||
.we2(BranchInstrE & ~StallM & ~FlushM),
|
||||
.bwe2(1'b1));
|
||||
|
||||
// if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage
|
||||
@ -84,15 +79,13 @@ module speculativegshare
|
||||
assign MatchF = BranchInstrF & ~FlushD & (IndexNextF == IndexF);
|
||||
assign MatchD = BranchInstrD & ~FlushE & (IndexNextF == IndexD);
|
||||
assign MatchE = BranchInstrE & ~FlushM & (IndexNextF == IndexE);
|
||||
assign MatchM = BranchInstrM & ~FlushW & (IndexNextF == IndexM);
|
||||
assign MatchNextX = MatchF | MatchD | MatchE | MatchM;
|
||||
assign MatchNextX = MatchF | MatchD | MatchE;
|
||||
|
||||
flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
|
||||
|
||||
assign ForwardNewDirPrediction = MatchF ? NewDirPredictionF :
|
||||
MatchD ? NewDirPredictionD :
|
||||
MatchE ? NewDirPredictionE :
|
||||
NewDirPredictionM;
|
||||
NewDirPredictionE ;
|
||||
|
||||
flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF);
|
||||
|
||||
@ -107,37 +100,44 @@ module speculativegshare
|
||||
|
||||
flopenr #(2) NewPredDReg(clk, reset, ~StallD, NewDirPredictionF, NewDirPredictionD);
|
||||
satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
|
||||
flopenr #(2) NewPredMReg(clk, reset, ~StallM, NewDirPredictionE, NewDirPredictionM);
|
||||
|
||||
// PCSrc pipeline
|
||||
flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
|
||||
flopenrc #(1) PCSrcWReg(clk, reset, FlushW, ~StallW, PCSrcM, PCSrcW);
|
||||
|
||||
// GHR pipeline
|
||||
assign GHRNextF = FlushD ? GHRNextD[k:1] :
|
||||
BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} :
|
||||
GHRF;
|
||||
// this version fails the regression test do to pessimistic x propagation.
|
||||
// assign GHRNextF = FlushD | DirPredictionWrongE ? GHRNextD[k-1:0] :
|
||||
// BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} :
|
||||
// GHRF;
|
||||
|
||||
flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF);
|
||||
|
||||
assign GHRNextD = FlushD ? {GHRNextE, GHRNextE[0]} : {DirPredictionF[1], GHRF, GHRF[0]};
|
||||
flopenr #(k+2) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, OldGHRD);
|
||||
assign GHRD = WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], OldGHRD[k:1]} : // shift right
|
||||
WrongPredInstrClassD[0] & ~BranchInstrD ? OldGHRD[k-1:-1] : // shift left
|
||||
OldGHRD[k:0];
|
||||
always_comb begin
|
||||
if(FlushD | DirPredictionWrongE) begin
|
||||
GHRNextF = GHRNextD[k-1:0];
|
||||
end else if(BranchInstrF) GHRNextF = {DirPredictionF[1], GHRF[k-1:1]};
|
||||
else GHRNextF = GHRF;
|
||||
end
|
||||
|
||||
assign GHRNextE = FlushE ? GHRNextM : GHRD;
|
||||
flopenr #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE);
|
||||
assign GHRE = BranchInstrE ? {PCSrcE, OldGHRE[k-1:0]} : OldGHRE;
|
||||
flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF);
|
||||
flopenr #(1) GHRFExtraReg(clk, reset, (~StallF) | FlushD, GHRF[0], GHRExtraF);
|
||||
|
||||
assign GHRNextM = FlushM ? GHRNextW : GHRE;
|
||||
flopenr #(k+1) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM);
|
||||
// use with out instruction class prediction
|
||||
//assign GHRNextD = FlushD ? GHRNextE[k-1:0] : GHRF[k-1:0];
|
||||
// with instruction class prediction
|
||||
assign GHRNextD = (FlushD | DirPredictionWrongE) ? GHRNextE[k-1:0] :
|
||||
WrongPredInstrClassD[0] & BranchInstrD ? {DirPredictionD[1], GHRF[k-1:1]} : // shift right
|
||||
WrongPredInstrClassD[0] & ~BranchInstrD ? {GHRF[k-2:0], GHRExtraF}: // shift left
|
||||
GHRF[k-1:0];
|
||||
|
||||
assign GHRNextW = FlushW ? GHRW : GHRM;
|
||||
flopenr #(k+1) GHRWReg(clk, reset, (BranchInstrM & ~StallW) | FlushW, GHRNextW, GHRW);
|
||||
flopenr #(k) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD);
|
||||
|
||||
assign GHRNextE = BranchInstrE & ~FlushM ? {PCSrcE, GHRD[k-2:0]} : // if the branch is not flushed
|
||||
FlushE ? GHRE : // branch is flushed
|
||||
GHRD;
|
||||
flopenr #(k) GHREReg(clk, reset, (BranchInstrE & ~StallE) | FlushE, GHRNextE, GHRE);
|
||||
|
||||
//assign GHRNextM = FlushM ? GHRM : GHRE;
|
||||
//flopenr #(k) GHRMReg(clk, reset, (BranchInstrM & ~StallM) | FlushM, GHRNextM, GHRM);
|
||||
|
||||
//assign GHRNextW = FlushW ? GHRW : GHRM;
|
||||
//flopenr #(k) GHRWReg(clk, reset, (BranchInstrW & ~StallW) | FlushW, GHRNextW, GHRW);
|
||||
|
||||
assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
|
||||
|
||||
flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);
|
||||
|
||||
endmodule
|
||||
@ -28,19 +28,17 @@
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module twoBitPredictor
|
||||
#(parameter int k = 10
|
||||
)
|
||||
(input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM,
|
||||
input logic FlushD, FlushE, FlushM,
|
||||
input logic [`XLEN-1:0] PCNextF, PCM,
|
||||
output logic [1:0] DirPredictionF,
|
||||
output logic DirPredictionWrongE,
|
||||
input logic BranchInstrE, BranchInstrM,
|
||||
input logic PCSrcE
|
||||
);
|
||||
module twoBitPredictor #(parameter k = 10) (
|
||||
input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM,
|
||||
input logic FlushD, FlushE, FlushM,
|
||||
input logic [`XLEN-1:0] PCNextF, PCM,
|
||||
output logic [1:0] DirPredictionF,
|
||||
output logic DirPredictionWrongE,
|
||||
input logic BranchInstrE, BranchInstrM,
|
||||
input logic PCSrcE
|
||||
);
|
||||
|
||||
logic [k-1:0] IndexNextF, IndexM;
|
||||
logic [1:0] PredictionMemory;
|
||||
@ -56,7 +54,7 @@ module twoBitPredictor
|
||||
assign IndexM = {PCM[k+1] ^ PCM[1], PCM[k:2]};
|
||||
|
||||
|
||||
ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk),
|
||||
ram2p1r1wbe #(2**k, 2) PHT(.clk(clk),
|
||||
.ce1(~StallF), .ce2(~StallM & ~FlushM),
|
||||
.ra1(IndexNextF),
|
||||
.rd1(DirPredictionF),
|
||||
@ -1,123 +0,0 @@
|
||||
///////////////////////////////////////////
|
||||
// globalHistoryPredictor.sv
|
||||
//
|
||||
// Written: Shreya Sanghai
|
||||
// Email: ssanghai@hmc.edu
|
||||
// Created: March 16, 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Global History Branch predictor with parameterized global history register
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module globalHistoryPredictor
|
||||
#(parameter int k = 10
|
||||
)
|
||||
(input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallE,
|
||||
input logic [`XLEN-1:0] PCNextF,
|
||||
output logic [1:0] BPPredF,
|
||||
// update
|
||||
input logic [4:0] InstrClassE,
|
||||
input logic [4:0] BPInstrClassE,
|
||||
input logic [4:0] BPInstrClassD,
|
||||
input logic [4:0] BPInstrClassF,
|
||||
input logic BPPredDirWrongE,
|
||||
|
||||
input logic [`XLEN-1:0] PCE,
|
||||
input logic PCSrcE,
|
||||
input logic [1:0] UpdateBPPredE
|
||||
|
||||
);
|
||||
logic [k+1:0] GHR, GHRNext;
|
||||
logic [k-1:0] PHTUpdateAdr, PHTUpdateAdr0, PHTUpdateAdr1;
|
||||
logic PHTUpdateEN;
|
||||
logic BPClassWrongNonCFI;
|
||||
logic BPClassWrongCFI;
|
||||
logic BPClassRightNonCFI;
|
||||
logic BPClassRightBPWrong;
|
||||
logic BPClassRightBPRight;
|
||||
|
||||
logic [6:0] GHRMuxSel;
|
||||
logic GHRUpdateEN;
|
||||
logic [k-1:0] GHRLookup;
|
||||
|
||||
assign BPClassRightNonCFI = ~BPInstrClassE[0] & ~InstrClassE[0];
|
||||
assign BPClassWrongCFI = ~BPInstrClassE[0] & InstrClassE[0];
|
||||
assign BPClassWrongNonCFI = BPInstrClassE[0] & ~InstrClassE[0];
|
||||
assign BPClassRightBPWrong = BPInstrClassE[0] & InstrClassE[0] & BPPredDirWrongE;
|
||||
assign BPClassRightBPRight = BPInstrClassE[0] & InstrClassE[0] & ~BPPredDirWrongE;
|
||||
|
||||
|
||||
// GHR update selection, 1 hot encoded.
|
||||
assign GHRMuxSel[0] = ~BPInstrClassF[0] & (BPClassRightNonCFI | BPClassRightBPRight);
|
||||
assign GHRMuxSel[1] = BPClassWrongCFI & ~BPInstrClassD[0];
|
||||
assign GHRMuxSel[2] = BPClassWrongNonCFI & ~BPInstrClassD[0];
|
||||
assign GHRMuxSel[3] = (BPClassRightBPWrong & ~BPInstrClassD[0]) | (BPClassWrongCFI & BPInstrClassD[0]);
|
||||
assign GHRMuxSel[4] = BPClassWrongNonCFI & BPInstrClassD[0];
|
||||
assign GHRMuxSel[5] = InstrClassE[0] & BPClassRightBPWrong & BPInstrClassD[0];
|
||||
assign GHRMuxSel[6] = BPInstrClassF[0] & (BPClassRightNonCFI | (InstrClassE[0] & BPClassRightBPRight));
|
||||
assign GHRUpdateEN = (| GHRMuxSel[5:1] & ~StallE) | GHRMuxSel[6] & ~StallF;
|
||||
|
||||
// hoping this created a AND-OR mux.
|
||||
always_comb begin
|
||||
case (GHRMuxSel)
|
||||
7'b000_0001: GHRNext = GHR[k-1+2:0]; // no change
|
||||
7'b000_0010: GHRNext = {GHR[k-2+2:0], PCSrcE}; // branch update
|
||||
7'b000_0100: GHRNext = {1'b0, GHR[k+1:1]}; // repair 1
|
||||
7'b000_1000: GHRNext = {GHR[k-1+2:1], PCSrcE}; // branch update with mis prediction correction
|
||||
7'b001_0000: GHRNext = {2'b00, GHR[k+1:2]}; // repair 2
|
||||
7'b010_0000: GHRNext = {1'b0, GHR[k+1:2], PCSrcE}; // branch update + repair 1
|
||||
7'b100_0000: GHRNext = {GHR[k-2+2:0], BPPredF[1]}; // speculative update
|
||||
default: GHRNext = GHR[k-1+2:0];
|
||||
endcase
|
||||
end
|
||||
|
||||
flopenr #(k+2) GlobalHistoryRegister(.clk(clk),
|
||||
.reset(reset),
|
||||
.en((GHRUpdateEN)),
|
||||
.d(GHRNext),
|
||||
.q(GHR));
|
||||
|
||||
// if actively updating the GHR at the time of prediction we want to us
|
||||
// GHRNext as the lookup rather than GHR.
|
||||
|
||||
assign PHTUpdateAdr0 = InstrClassE[0] ? GHR[k:1] : GHR[k-1:0];
|
||||
assign PHTUpdateAdr1 = InstrClassE[0] ? GHR[k+1:2] : GHR[k:1];
|
||||
assign PHTUpdateAdr = BPInstrClassD[0] ? PHTUpdateAdr1 : PHTUpdateAdr0;
|
||||
assign PHTUpdateEN = InstrClassE[0] & ~StallE;
|
||||
|
||||
assign GHRLookup = |GHRMuxSel[6:1] ? GHRNext[k-1:0] : GHR[k-1:0];
|
||||
|
||||
// Make Prediction by reading the correct address in the PHT and also update the new address in the PHT
|
||||
ram2p1r1wb #(k, 2) PHT(.clk(clk),
|
||||
.reset(reset),
|
||||
//.RA1(GHR[k-1:0]),
|
||||
.ra1(GHRLookup),
|
||||
.rd1(BPPredF),
|
||||
.ren1(~StallF),
|
||||
.wa2(PHTUpdateAdr),
|
||||
.wd2(UpdateBPPredE),
|
||||
.wen2(PHTUpdateEN),
|
||||
.bwe2(2'b11));
|
||||
|
||||
endmodule
|
||||
@ -44,13 +44,14 @@ module ifu (
|
||||
output logic [2:0] IFUHBURST, // Bus burst from IFU to EBU
|
||||
output logic [1:0] IFUHTRANS, // Bus transaction type from IFU to EBU
|
||||
|
||||
output logic [`XLEN-1:0] PCF, // Fetch stage instruction address
|
||||
output logic [`XLEN-1:0] PCFSpill, // PCF with possible + 2 to handle spill to HPTW
|
||||
// Execute
|
||||
output logic [`XLEN-1:0] PCLinkE, // The address following the branch instruction. (AKA Fall through address)
|
||||
input logic PCSrcE, // Executation stage branch is taken
|
||||
input logic [`XLEN-1:0] IEUAdrE, // The branch/jump target address
|
||||
output logic [`XLEN-1:0] PCE, // Execution stage instruction address
|
||||
output logic BPPredWrongE, // Prediction is wrong
|
||||
output logic BPPredWrongM, // Prediction is wrong
|
||||
// Mem
|
||||
output logic CommittedF, // I$ or bus memory operation started, delay interrupts
|
||||
input logic [`XLEN-1:0] UnalignedPCNextF, // The next PCF, but not aligned to 2 bytes.
|
||||
@ -60,6 +61,7 @@ module ifu (
|
||||
output logic [`XLEN-1:0] PCM, // Memory stage instruction address
|
||||
// branch predictor
|
||||
output logic [3:0] InstrClassM, // The valid instruction class. 1-hot encoded as jalr, ret, jr (not ret), j, br
|
||||
output logic JumpOrTakenBranchM,
|
||||
output logic DirPredictionWrongM, // Prediction direction is wrong
|
||||
output logic BTBPredPCWrongM, // Prediction target wrong
|
||||
output logic RASPredPCWrongM, // RAS prediction is wrong
|
||||
@ -95,19 +97,19 @@ module ifu (
|
||||
logic BranchMisalignedFaultE; // Branch target not aligned to 4 bytes if no compressed allowed (2 bytes if allowed)
|
||||
logic [`XLEN-1:0] PCPlus2or4F; // PCF + 2 (CompressedF) or PCF + 4 (Non-compressed)
|
||||
logic [`XLEN-1:0] PCNextFSpill; // Next PCF after possible + 2 to handle spill
|
||||
logic [`XLEN-1:0] PCFSpill; // PCF with possible + 2 to handle spill
|
||||
logic [`XLEN-1:0] PCLinkD; // PCF2or4F delayed 1 cycle. This is next PC after a control flow instruction (br or j)
|
||||
logic [`XLEN-1:2] PCPlus4F; // PCPlus4F is always PCF + 4. Fancy way to compute PCPlus2or4F
|
||||
logic [`XLEN-1:0] PCD; // Decode stage instruction address
|
||||
logic [`XLEN-1:0] NextValidPCE; // The PC of the next valid instruction in the pipeline after csr write or fence
|
||||
logic [`PA_BITS-1:0] PCPF; // Physical address after address translation
|
||||
logic [`XLEN-1:0] PCF; // Fetch stage instruction address
|
||||
logic [`PA_BITS-1:0] PCPF; // Physical address after address translation
|
||||
logic [`XLEN+1:0] PCFExt; //
|
||||
|
||||
logic [31:0] IROMInstrF; // Instruction from the IROM
|
||||
logic [31:0] ICacheInstrF; // Instruction from the I$
|
||||
logic [31:0] InstrRawF; // Instruction from the IROM, I$, or bus
|
||||
logic CompressedF; // The fetched instruction is compressed
|
||||
logic [31:0] PostSpillInstrRawF; // Fetch instruction after merge two halves of spill
|
||||
logic [31:0] PostSpillInstrRawF; // Fetch instruction after merge two halves of spill
|
||||
logic [31:0] InstrRawD; // Non-decompressed instruction in the Decode stage
|
||||
|
||||
logic [1:0] IFURWF; // IFU alreays read IFURWF = 10
|
||||
@ -115,7 +117,7 @@ module ifu (
|
||||
logic [31:0] NextInstrD, NextInstrE; // Instruction into the next stage after possible stage flush
|
||||
|
||||
|
||||
logic CacheableF; // PMA indicates isntruction address is cacheable
|
||||
logic CacheableF; // PMA indicates instruction address is cacheable
|
||||
logic SelNextSpillF; // In a spill, stall pipeline and gate local stallF
|
||||
logic BusStall; // Bus interface busy with multicycle operation
|
||||
logic ICacheStallF; // I$ busy with multicycle operation
|
||||
@ -134,7 +136,7 @@ module ifu (
|
||||
/////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
if(`C_SUPPORTED) begin : Spill
|
||||
spill #(`ICACHE) spill(.clk, .reset, .StallD, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF,
|
||||
spill #(`ICACHE_SUPPORTED) spill(.clk, .reset, .StallD, .FlushD, .PCF, .PCPlus4F, .PCNextF, .InstrRawF,
|
||||
.InstrDAPageFaultF, .IFUCacheBusStallD, .ITLBMissF, .PCNextFSpill, .PCFSpill, .SelNextSpillF, .PostSpillInstrRawF, .CompressedF);
|
||||
end else begin : NoSpill
|
||||
assign PCNextFSpill = PCNextF;
|
||||
@ -208,13 +210,13 @@ module ifu (
|
||||
end else begin
|
||||
assign IFURWF = 2'b10;
|
||||
end
|
||||
if (`BUS) begin : bus
|
||||
if (`BUS_SUPPORTED) begin : bus
|
||||
// **** must fix words per line vs beats per line as in lsu.
|
||||
localparam integer WORDSPERLINE = `ICACHE ? `ICACHE_LINELENINBITS/`XLEN : 1;
|
||||
localparam integer LOGBWPL = `ICACHE ? $clog2(WORDSPERLINE) : 1;
|
||||
if(`ICACHE) begin : icache
|
||||
localparam integer LINELEN = `ICACHE ? `ICACHE_LINELENINBITS : `XLEN;
|
||||
localparam integer LLENPOVERAHBW = `LLEN / `AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
|
||||
localparam WORDSPERLINE = `ICACHE_SUPPORTED ? `ICACHE_LINELENINBITS/`XLEN : 1;
|
||||
localparam LOGBWPL = `ICACHE_SUPPORTED ? $clog2(WORDSPERLINE) : 1;
|
||||
if(`ICACHE_SUPPORTED) begin : icache
|
||||
localparam LINELEN = `ICACHE_SUPPORTED ? `ICACHE_LINELENINBITS : `XLEN;
|
||||
localparam LLENPOVERAHBW = `LLEN / `AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
|
||||
logic [LINELEN-1:0] FetchBuffer;
|
||||
logic [`PA_BITS-1:0] ICacheBusAdr;
|
||||
logic ICacheBusAck;
|
||||
@ -322,12 +324,12 @@ module ifu (
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// Branch and Jump Predictor
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
if (`BPRED_ENABLED) begin : bpred
|
||||
if (`BPRED_SUPPORTED) begin : bpred
|
||||
bpred bpred(.clk, .reset,
|
||||
.StallF, .StallD, .StallE, .StallM, .StallW,
|
||||
.FlushD, .FlushE, .FlushM, .FlushW,
|
||||
.InstrD, .PCNextF, .PCPlus2or4F, .PCNext1F, .PCE, .PCM, .PCSrcE, .IEUAdrE, .PCF, .NextValidPCE,
|
||||
.PCD, .PCLinkE, .InstrClassM, .BPPredWrongE,
|
||||
.PCD, .PCLinkE, .InstrClassM, .BPPredWrongE, .PostSpillInstrRawF, .JumpOrTakenBranchM, .BPPredWrongM,
|
||||
.DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM);
|
||||
|
||||
end else begin : bpred
|
||||
|
||||
@ -1,130 +0,0 @@
|
||||
///////////////////////////////////////////
|
||||
// globalHistoryPredictor.sv
|
||||
//
|
||||
// Written: Shreya Sanghai
|
||||
// Email: ssanghai@hmc.edu
|
||||
// Created: March 16, 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Gshare predictor with parameterized global history register
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
module oldgsharepredictor
|
||||
(input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM, StallW,
|
||||
input logic FlushD, FlushE, FlushM, FlushW,
|
||||
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
|
||||
output logic [1:0] DirPredictionF,
|
||||
// update
|
||||
input logic [4:0] InstrClassE,
|
||||
input logic [4:0] BPInstrClassE,
|
||||
input logic [4:0] BPInstrClassD,
|
||||
input logic [4:0] BPInstrClassF,
|
||||
output logic DirPredictionWrongE,
|
||||
|
||||
input logic PCSrcE
|
||||
|
||||
);
|
||||
logic [`BPRED_SIZE+1:0] GHR, GHRNext;
|
||||
logic [`BPRED_SIZE-1:0] PHTUpdateAdr, PHTUpdateAdr0, PHTUpdateAdr1;
|
||||
logic PHTUpdateEN;
|
||||
logic BPClassWrongNonCFI;
|
||||
logic BPClassWrongCFI;
|
||||
logic BPClassRightNonCFI;
|
||||
logic BPClassRightBPWrong;
|
||||
logic BPClassRightBPRight;
|
||||
logic [1:0] DirPredictionD, DirPredictionE;
|
||||
logic [1:0] NewDirPredictionE;
|
||||
|
||||
logic [6:0] GHRMuxSel;
|
||||
logic GHRUpdateEN;
|
||||
logic [`BPRED_SIZE-1:0] GHRLookup;
|
||||
|
||||
assign BPClassRightNonCFI = ~BPInstrClassE[0] & ~InstrClassE[0];
|
||||
assign BPClassWrongCFI = ~BPInstrClassE[0] & InstrClassE[0];
|
||||
assign BPClassWrongNonCFI = BPInstrClassE[0] & ~InstrClassE[0];
|
||||
assign BPClassRightBPWrong = BPInstrClassE[0] & InstrClassE[0] & DirPredictionWrongE;
|
||||
assign BPClassRightBPRight = BPInstrClassE[0] & InstrClassE[0] & ~DirPredictionWrongE;
|
||||
|
||||
|
||||
// GHR update selection, 1 hot encoded.
|
||||
assign GHRMuxSel[0] = ~BPInstrClassF[0] & (BPClassRightNonCFI | BPClassRightBPRight);
|
||||
assign GHRMuxSel[1] = BPClassWrongCFI & ~BPInstrClassD[0];
|
||||
assign GHRMuxSel[2] = BPClassWrongNonCFI & ~BPInstrClassD[0];
|
||||
assign GHRMuxSel[3] = (BPClassRightBPWrong & ~BPInstrClassD[0]) | (BPClassWrongCFI & BPInstrClassD[0]);
|
||||
assign GHRMuxSel[4] = BPClassWrongNonCFI & BPInstrClassD[0];
|
||||
assign GHRMuxSel[5] = InstrClassE[0] & BPClassRightBPWrong & BPInstrClassD[0];
|
||||
assign GHRMuxSel[6] = BPInstrClassF[0] & (BPClassRightNonCFI | (InstrClassE[0] & BPClassRightBPRight));
|
||||
assign GHRUpdateEN = (| GHRMuxSel[5:1] & ~StallE) | GHRMuxSel[6] & ~StallF;
|
||||
|
||||
// hoping this created a AND-OR mux.
|
||||
always_comb begin
|
||||
case (GHRMuxSel)
|
||||
7'b000_0001: GHRNext = GHR[`BPRED_SIZE-1+2:0]; // no change
|
||||
7'b000_0010: GHRNext = {GHR[`BPRED_SIZE-2+2:0], PCSrcE}; // branch update
|
||||
7'b000_0100: GHRNext = {1'b0, GHR[`BPRED_SIZE+1:1]}; // repair 1
|
||||
7'b000_1000: GHRNext = {GHR[`BPRED_SIZE-1+2:1], PCSrcE}; // branch update with mis prediction correction
|
||||
7'b001_0000: GHRNext = {2'b00, GHR[`BPRED_SIZE+1:2]}; // repair 2
|
||||
7'b010_0000: GHRNext = {1'b0, GHR[`BPRED_SIZE+1:2], PCSrcE}; // branch update + repair 1
|
||||
7'b100_0000: GHRNext = {GHR[`BPRED_SIZE-2+2:0], DirPredictionF[1]}; // speculative update
|
||||
default: GHRNext = GHR[`BPRED_SIZE-1+2:0];
|
||||
endcase
|
||||
end
|
||||
|
||||
flopenr #(`BPRED_SIZE+2) GlobalHistoryRegister(.clk(clk),
|
||||
.reset(reset),
|
||||
.en((GHRUpdateEN)),
|
||||
.d(GHRNext),
|
||||
.q(GHR));
|
||||
|
||||
// if actively updating the GHR at the time of prediction we want to us
|
||||
// GHRNext as the lookup rather than GHR.
|
||||
|
||||
assign PHTUpdateAdr0 = InstrClassE[0] ? GHR[`BPRED_SIZE:1] : GHR[`BPRED_SIZE-1:0];
|
||||
assign PHTUpdateAdr1 = InstrClassE[0] ? GHR[`BPRED_SIZE+1:2] : GHR[`BPRED_SIZE:1];
|
||||
assign PHTUpdateAdr = BPInstrClassD[0] ? PHTUpdateAdr1 : PHTUpdateAdr0;
|
||||
assign PHTUpdateEN = InstrClassE[0] & ~StallE;
|
||||
|
||||
assign GHRLookup = |GHRMuxSel[6:1] ? GHRNext[`BPRED_SIZE-1:0] : GHR[`BPRED_SIZE-1:0];
|
||||
|
||||
// Make Prediction by reading the correct address in the PHT and also update the new address in the PHT
|
||||
ram2p1r1wb #(`BPRED_SIZE, 2) PHT(.clk(clk),
|
||||
.reset(reset),
|
||||
//.RA1(GHR[`BPRED_SIZE-1:0]),
|
||||
.ra1(GHRLookup ^ PCNextF[`BPRED_SIZE:1]),
|
||||
.rd1(DirPredictionF),
|
||||
.ren1(~StallF),
|
||||
.wa2(PHTUpdateAdr ^ PCE[`BPRED_SIZE:1]),
|
||||
.wd2(NewDirPredictionE),
|
||||
.wen2(PHTUpdateEN),
|
||||
.bwe2(2'b11));
|
||||
|
||||
// DirPrediction pipeline
|
||||
flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD);
|
||||
flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE);
|
||||
|
||||
// New prediction pipeline
|
||||
satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
|
||||
|
||||
assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & InstrClassE[0];
|
||||
|
||||
endmodule // gsharePredictor
|
||||
@ -1,130 +0,0 @@
|
||||
///////////////////////////////////////////
|
||||
// globalHistoryPredictor.sv
|
||||
//
|
||||
// Written: Shreya Sanghai
|
||||
// Email: ssanghai@hmc.edu
|
||||
// Created: March 16, 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Gshare predictor with parameterized global history register
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
module oldgsharepredictor2
|
||||
(input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM, StallW,
|
||||
input logic FlushD, FlushE, FlushM, FlushW,
|
||||
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
|
||||
output logic [1:0] DirPredictionF,
|
||||
// update
|
||||
input logic [4:0] InstrClassE,
|
||||
input logic [4:0] BPInstrClassE,
|
||||
input logic [4:0] BPInstrClassD,
|
||||
input logic [4:0] BPInstrClassF,
|
||||
output logic DirPredictionWrongE,
|
||||
|
||||
input logic PCSrcE
|
||||
|
||||
);
|
||||
logic [`BPRED_SIZE+1:0] GHR, GHRNext;
|
||||
logic [`BPRED_SIZE-1:0] PHTUpdateAdr, PHTUpdateAdr0, PHTUpdateAdr1;
|
||||
logic PHTUpdateEN;
|
||||
logic BPClassWrongNonCFI;
|
||||
logic BPClassWrongCFI;
|
||||
logic BPClassRightNonCFI;
|
||||
logic BPClassRightBPWrong;
|
||||
logic BPClassRightBPRight;
|
||||
logic [1:0] DirPredictionD, DirPredictionE;
|
||||
logic [1:0] NewDirPredictionE;
|
||||
|
||||
logic [6:0] GHRMuxSel;
|
||||
logic GHRUpdateEN;
|
||||
logic [`BPRED_SIZE-1:0] GHRLookup;
|
||||
|
||||
assign BPClassRightNonCFI = ~BPInstrClassE[0] & ~InstrClassE[0];
|
||||
assign BPClassWrongCFI = ~BPInstrClassE[0] & InstrClassE[0];
|
||||
assign BPClassWrongNonCFI = BPInstrClassE[0] & ~InstrClassE[0];
|
||||
assign BPClassRightBPWrong = BPInstrClassE[0] & InstrClassE[0] & DirPredictionWrongE;
|
||||
assign BPClassRightBPRight = BPInstrClassE[0] & InstrClassE[0] & ~DirPredictionWrongE;
|
||||
|
||||
|
||||
// GHR update selection, 1 hot encoded.
|
||||
assign GHRMuxSel[0] = ~BPInstrClassF[0] & (BPClassRightNonCFI | BPClassRightBPRight);
|
||||
assign GHRMuxSel[1] = BPClassWrongCFI & ~BPInstrClassD[0];
|
||||
assign GHRMuxSel[2] = BPClassWrongNonCFI & ~BPInstrClassD[0];
|
||||
assign GHRMuxSel[3] = (BPClassRightBPWrong & ~BPInstrClassD[0]) | (BPClassWrongCFI & BPInstrClassD[0]);
|
||||
assign GHRMuxSel[4] = BPClassWrongNonCFI & BPInstrClassD[0];
|
||||
assign GHRMuxSel[5] = InstrClassE[0] & BPClassRightBPWrong & BPInstrClassD[0];
|
||||
assign GHRMuxSel[6] = BPInstrClassF[0] & (BPClassRightNonCFI | (InstrClassE[0] & BPClassRightBPRight));
|
||||
assign GHRUpdateEN = (| GHRMuxSel[5:1] & ~StallE) | GHRMuxSel[6] & ~StallF;
|
||||
|
||||
// hoping this created a AND-OR mux.
|
||||
always_comb begin
|
||||
case (GHRMuxSel)
|
||||
7'b000_0001: GHRNext = GHR[`BPRED_SIZE-1+2:0]; // no change
|
||||
7'b000_0010: GHRNext = {GHR[`BPRED_SIZE-2+2:0], PCSrcE}; // branch update
|
||||
7'b000_0100: GHRNext = {1'b0, GHR[`BPRED_SIZE+1:1]}; // repair 1
|
||||
7'b000_1000: GHRNext = {GHR[`BPRED_SIZE-1+2:1], PCSrcE}; // branch update with mis prediction correction
|
||||
7'b001_0000: GHRNext = {2'b00, GHR[`BPRED_SIZE+1:2]}; // repair 2
|
||||
7'b010_0000: GHRNext = {1'b0, GHR[`BPRED_SIZE+1:2], PCSrcE}; // branch update + repair 1
|
||||
7'b100_0000: GHRNext = {GHR[`BPRED_SIZE-2+2:0], DirPredictionF[1]}; // speculative update
|
||||
default: GHRNext = GHR[`BPRED_SIZE-1+2:0];
|
||||
endcase
|
||||
end
|
||||
|
||||
flopenr #(`BPRED_SIZE+2) GlobalHistoryRegister(.clk(clk),
|
||||
.reset(reset),
|
||||
.en((GHRUpdateEN)),
|
||||
.d(GHRNext),
|
||||
.q(GHR));
|
||||
|
||||
// if actively updating the GHR at the time of prediction we want to us
|
||||
// GHRNext as the lookup rather than GHR.
|
||||
|
||||
assign PHTUpdateAdr0 = InstrClassE[0] ? GHR[`BPRED_SIZE:1] : GHR[`BPRED_SIZE-1:0];
|
||||
assign PHTUpdateAdr1 = InstrClassE[0] ? GHR[`BPRED_SIZE+1:2] : GHR[`BPRED_SIZE:1];
|
||||
assign PHTUpdateAdr = BPInstrClassD[0] ? PHTUpdateAdr1 : PHTUpdateAdr0;
|
||||
assign PHTUpdateEN = InstrClassE[0] & ~StallE;
|
||||
|
||||
assign GHRLookup = |GHRMuxSel[6:1] ? GHRNext[`BPRED_SIZE-1:0] : GHR[`BPRED_SIZE-1:0];
|
||||
|
||||
// Make Prediction by reading the correct address in the PHT and also update the new address in the PHT
|
||||
ram2p1r1wb #(`BPRED_SIZE, 2) PHT(.clk(clk),
|
||||
.reset(reset),
|
||||
//.RA1(GHR[`BPRED_SIZE-1:0]),
|
||||
.ra1(GHRLookup ^ PCNextF[`BPRED_SIZE:1]),
|
||||
.rd1(DirPredictionF),
|
||||
.ren1(~StallF),
|
||||
.wa2(PHTUpdateAdr ^ PCE[`BPRED_SIZE:1]),
|
||||
.wd2(NewDirPredictionE),
|
||||
.wen2(PHTUpdateEN),
|
||||
.bwe2(2'b11));
|
||||
|
||||
// DirPrediction pipeline
|
||||
flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD);
|
||||
flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE);
|
||||
|
||||
// New prediction pipeline
|
||||
satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
|
||||
|
||||
assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & InstrClassE[0];
|
||||
|
||||
endmodule // gsharePredictor
|
||||
@ -1,132 +0,0 @@
|
||||
///////////////////////////////////////////
|
||||
// globalHistoryPredictor.sv
|
||||
//
|
||||
// Written: Shreya Sanghai
|
||||
// Email: ssanghai@hmc.edu
|
||||
// Created: March 16, 2021
|
||||
// Modified:
|
||||
//
|
||||
// Purpose: Global History Branch predictor with parameterized global history register
|
||||
//
|
||||
// A component of the CORE-V-WALLY configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021-23 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
|
||||
module speculativeglobalhistory
|
||||
#(parameter int k = 10
|
||||
)
|
||||
(input logic clk,
|
||||
input logic reset,
|
||||
input logic StallF, StallD, StallE, StallM, StallW,
|
||||
input logic FlushD, FlushE, FlushM, FlushW,
|
||||
// input logic [`XLEN-1:0] LookUpPC,
|
||||
output logic [1:0] DirPredictionF,
|
||||
output logic DirPredictionWrongE,
|
||||
// update
|
||||
input logic [`XLEN-1:0] PCNextF, PCF, PCD, PCE, PCM,
|
||||
input logic BranchInstrF, BranchInstrD, BranchInstrE, BranchInstrM, BranchInstrW,
|
||||
input logic PCSrcE
|
||||
);
|
||||
|
||||
logic MatchF, MatchD, MatchE, MatchM, MatchW;
|
||||
logic MatchNextX, MatchXF;
|
||||
|
||||
logic [1:0] TableDirPredictionF, DirPredictionD, DirPredictionE;
|
||||
logic [1:0] NewDirPredictionF, NewDirPredictionD, NewDirPredictionE, NewDirPredictionM, NewDirPredictionW;
|
||||
|
||||
logic [k-1:0] GHRF;
|
||||
logic [k:0] GHRD, OldGHRE, GHRE, GHRM, GHRW;
|
||||
logic [k-1:0] GHRNextF;
|
||||
logic [k:0] GHRNextD, GHRNextE, GHRNextM, GHRNextW;
|
||||
logic PCSrcM, PCSrcW;
|
||||
logic [`XLEN-1:0] PCW;
|
||||
|
||||
logic [1:0] ForwardNewDirPrediction, ForwardDirPredictionF;
|
||||
|
||||
|
||||
ram2p1r1wbefix #(2**k, 2) PHT(.clk(clk),
|
||||
.ce1(~StallF | reset), .ce2(~StallW & ~FlushW),
|
||||
.ra1(GHRNextF),
|
||||
.rd1(TableDirPredictionF),
|
||||
.wa2(GHRW[k-1:0]),
|
||||
.wd2(NewDirPredictionW),
|
||||
.we2(BranchInstrW & ~StallW & ~FlushW),
|
||||
.bwe2(1'b1));
|
||||
|
||||
// if there are non-flushed branches in the pipeline we need to forward the prediction from that stage to the NextF demi stage
|
||||
// and then register for use in the Fetch stage.
|
||||
assign MatchF = BranchInstrF & ~FlushD & (GHRNextF == GHRF);
|
||||
assign MatchD = BranchInstrD & ~FlushE & (GHRNextF == GHRD[k-1:0]);
|
||||
assign MatchE = BranchInstrE & ~FlushM & (GHRNextF == GHRE[k-1:0]);
|
||||
assign MatchM = BranchInstrM & ~FlushW & (GHRNextF == GHRM[k-1:0]);
|
||||
assign MatchW = BranchInstrW & (GHRNextF == GHRW[k-1:0]);
|
||||
assign MatchNextX = MatchF | MatchD | MatchE | MatchM | MatchW;
|
||||
|
||||
flopenr #(1) MatchReg(clk, reset, ~StallF, MatchNextX, MatchXF);
|
||||
|
||||
assign ForwardNewDirPrediction = MatchF ? NewDirPredictionF :
|
||||
MatchD ? NewDirPredictionD :
|
||||
MatchE ? NewDirPredictionE :
|
||||
MatchM ? NewDirPredictionM :
|
||||
NewDirPredictionW;
|
||||
|
||||
flopenr #(2) ForwardDirPredicitonReg(clk, reset, ~StallF, ForwardNewDirPrediction, ForwardDirPredictionF);
|
||||
|
||||
assign DirPredictionF = MatchXF ? ForwardDirPredictionF : TableDirPredictionF;
|
||||
|
||||
// DirPrediction pipeline
|
||||
flopenr #(2) PredictionRegD(clk, reset, ~StallD, DirPredictionF, DirPredictionD);
|
||||
flopenr #(2) PredictionRegE(clk, reset, ~StallE, DirPredictionD, DirPredictionE);
|
||||
|
||||
// New prediction pipeline
|
||||
satCounter2 BPDirUpdateF(.BrDir(DirPredictionF[1]), .OldState(DirPredictionF), .NewState(NewDirPredictionF));
|
||||
flopenr #(2) NewPredDReg(clk, reset, ~StallD, NewDirPredictionF, NewDirPredictionD);
|
||||
satCounter2 BPDirUpdateE(.BrDir(PCSrcE), .OldState(DirPredictionE), .NewState(NewDirPredictionE));
|
||||
flopenr #(2) NewPredMReg(clk, reset, ~StallM, NewDirPredictionE, NewDirPredictionM);
|
||||
flopenr #(2) NewPredWReg(clk, reset, ~StallW, NewDirPredictionM, NewDirPredictionW);
|
||||
|
||||
// PCSrc pipeline
|
||||
flopenrc #(1) PCSrcMReg(clk, reset, FlushM, ~StallM, PCSrcE, PCSrcM);
|
||||
flopenrc #(1) PCSrcWReg(clk, reset, FlushW, ~StallW, PCSrcM, PCSrcW);
|
||||
|
||||
// GHR pipeline
|
||||
assign GHRNextF = FlushD ? GHRNextD[k:1] :
|
||||
BranchInstrF ? {DirPredictionF[1], GHRF[k-1:1]} :
|
||||
GHRF;
|
||||
|
||||
flopenr #(k) GHRFReg(clk, reset, (~StallF) | FlushD, GHRNextF, GHRF);
|
||||
|
||||
assign GHRNextD = FlushD ? GHRNextE : {DirPredictionF[1], GHRF};
|
||||
flopenr #(k+1) GHRDReg(clk, reset, (~StallD) | FlushD, GHRNextD, GHRD);
|
||||
|
||||
assign GHRNextE = FlushE ? GHRNextM : GHRD;
|
||||
flopenr #(k+1) GHREReg(clk, reset, (~StallE) | FlushE, GHRNextE, OldGHRE);
|
||||
assign GHRE = BranchInstrE ? {PCSrcE, OldGHRE[k-1:0]} : OldGHRE;
|
||||
|
||||
assign GHRNextM = FlushM ? GHRNextW : GHRE;
|
||||
flopenr #(k+1) GHRMReg(clk, reset, (~StallM) | FlushM, GHRNextM, GHRM);
|
||||
|
||||
assign GHRNextW = FlushW ? GHRW : GHRM;
|
||||
flopenr #(k+1) GHRWReg(clk, reset, (BranchInstrM & ~StallW) | FlushW, GHRNextW, GHRW);
|
||||
|
||||
assign DirPredictionWrongE = PCSrcE != DirPredictionE[1] & BranchInstrE;
|
||||
|
||||
flopenr #(`XLEN) PCWReg(clk, reset, ~StallW, PCM, PCW);
|
||||
|
||||
endmodule
|
||||
@ -50,15 +50,15 @@ module spill #(
|
||||
output logic CompressedF); // The fetched instruction is compressed
|
||||
|
||||
// Spill threshold occurs when all the cache offset PC bits are 1 (except [0]). Without a cache this is just PCF[1]
|
||||
localparam integer SPILLTHRESHOLD = CACHE_ENABLED ? `ICACHE_LINELENINBITS/32 : 1;
|
||||
typedef enum logic [1:0] {STATE_READY, STATE_SPILL} statetype;
|
||||
statetype CurrState, NextState;
|
||||
localparam SPILLTHRESHOLD = CACHE_ENABLED ? `ICACHE_LINELENINBITS/32 : 1;
|
||||
logic [`XLEN-1:0] PCPlus2F;
|
||||
logic TakeSpillF;
|
||||
logic SpillF;
|
||||
logic SelSpillF;
|
||||
logic SpillSaveF;
|
||||
logic SpillSaveF;
|
||||
logic [15:0] InstrFirstHalf;
|
||||
typedef enum logic [1:0] {STATE_READY, STATE_SPILL} statetype;
|
||||
statetype CurrState, NextState;
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
// PC logic
|
||||
|
||||
@ -79,7 +79,7 @@ module lsu (
|
||||
input logic [`XLEN-1:0] SATP_REGW, // SATP (supervisor address translation and protection) CSR
|
||||
input logic STATUS_MXR, STATUS_SUM, STATUS_MPRV, // STATUS CSR bits: make executable readable, supervisor user memory, machine privilege
|
||||
input logic [1:0] STATUS_MPP, // Machine previous privilege mode
|
||||
input logic [`XLEN-1:0] PCF, // Fetch PC
|
||||
input logic [`XLEN-1:0] PCFSpill, // Fetch PC
|
||||
input logic ITLBMissF, // ITLB miss causes HPTW (hardware pagetable walker) walk
|
||||
input logic InstrDAPageFaultF, // ITLB hit needs to update dirty or access bits
|
||||
output logic [`XLEN-1:0] PTE, // Page table entry write to ITLB
|
||||
@ -152,7 +152,7 @@ module lsu (
|
||||
if(`VIRTMEM_SUPPORTED) begin : VIRTMEM_SUPPORTED
|
||||
hptw hptw(.clk, .reset, .MemRWM, .AtomicM, .ITLBMissF, .ITLBWriteF,
|
||||
.DTLBMissM, .DTLBWriteM, .InstrDAPageFaultF, .DataDAPageFaultM,
|
||||
.FlushW, .DCacheStallM, .SATP_REGW, .PCF,
|
||||
.FlushW, .DCacheStallM, .SATP_REGW, .PCFSpill,
|
||||
.STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_MPP, .PrivilegeModeW,
|
||||
.ReadDataM(ReadDataM[`XLEN-1:0]), // ReadDataM is LLEN, but HPTW only needs XLEN
|
||||
.WriteDataM, .Funct3M, .LSUFunct3M, .Funct7M, .LSUFunct7M,
|
||||
@ -206,7 +206,7 @@ module lsu (
|
||||
assign {LoadPageFaultM, StoreAmoPageFaultM} = '0;
|
||||
assign PAdrM = IHAdrM[`PA_BITS-1:0];
|
||||
assign CacheableM = 1'b1;
|
||||
assign SelDTIM = `DTIM_SUPPORTED & ~`BUS; // if no PMA then select dtim if there is a DTIM. If there is
|
||||
assign SelDTIM = `DTIM_SUPPORTED & ~`BUS_SUPPORTED; // if no PMA then select dtim if there is a DTIM. If there is
|
||||
// a bus then this is always 0. Cannot have both without PMA.
|
||||
end
|
||||
|
||||
@ -236,14 +236,14 @@ module lsu (
|
||||
.ReadDataWordM(DTIMReadDataWordM[`XLEN-1:0]), .ByteMaskM(ByteMaskM[`XLEN/8-1:0]));
|
||||
end else begin
|
||||
end
|
||||
if (`BUS) begin : bus
|
||||
if(`DCACHE) begin : dcache
|
||||
localparam integer LLENWORDSPERLINE = `DCACHE_LINELENINBITS/`LLEN; // Number of LLEN words in cacheline
|
||||
localparam integer LLENLOGBWPL = $clog2(LLENWORDSPERLINE); // Log2 of ^
|
||||
localparam integer BEATSPERLINE = `DCACHE_LINELENINBITS/`AHBW; // Number of AHBW words (beats) in cacheline
|
||||
localparam integer AHBWLOGBWPL = $clog2(BEATSPERLINE); // Log2 of ^
|
||||
localparam integer LINELEN = `DCACHE_LINELENINBITS; // Number of bits in cacheline
|
||||
localparam integer LLENPOVERAHBW = `LLEN / `AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
|
||||
if (`BUS_SUPPORTED) begin : bus
|
||||
if(`DCACHE_SUPPORTED) begin : dcache
|
||||
localparam LLENWORDSPERLINE = `DCACHE_LINELENINBITS/`LLEN; // Number of LLEN words in cacheline
|
||||
localparam LLENLOGBWPL = $clog2(LLENWORDSPERLINE); // Log2 of ^
|
||||
localparam BEATSPERLINE = `DCACHE_LINELENINBITS/`AHBW; // Number of AHBW words (beats) in cacheline
|
||||
localparam AHBWLOGBWPL = $clog2(BEATSPERLINE); // Log2 of ^
|
||||
localparam LINELEN = `DCACHE_LINELENINBITS; // Number of bits in cacheline
|
||||
localparam LLENPOVERAHBW = `LLEN / `AHBW; // Number of AHB beats in a LLEN word. AHBW cannot be larger than LLEN. (implementation limitation)
|
||||
|
||||
logic [LINELEN-1:0] FetchBuffer; // Temporary buffer to hold partially fetched cacheline
|
||||
logic [`PA_BITS-1:0] DCacheBusAdr; // Cacheline address to fetch or writeback.
|
||||
@ -251,10 +251,10 @@ module lsu (
|
||||
logic DCacheBusAck; // ahbcacheinterface completed fetch or writeback
|
||||
logic SelBusBeat; // ahbcacheinterface selects postion in cacheline with BeatCount
|
||||
logic [1:0] CacheBusRW; // Cache sends request to ahbcacheinterface
|
||||
logic [1:0] BusRW; // Uncached bus memory access
|
||||
logic [1:0] BusRW; // Uncached bus memory access
|
||||
logic CacheableOrFlushCacheM; // Memory address is cacheable or operation is a cache flush
|
||||
logic [1:0] CacheRWM; // Cache read (10), write (01), AMO (11)
|
||||
logic [1:0] CacheAtomicM; // Cache AMO
|
||||
logic [1:0] CacheAtomicM; // Cache AMO
|
||||
|
||||
assign BusRW = ~CacheableM & ~IgnoreRequestTLB & ~SelDTIM ? LSURWM : '0;
|
||||
assign CacheableOrFlushCacheM = CacheableM | FlushDCacheM;
|
||||
|
||||
@ -34,7 +34,7 @@
|
||||
module hptw (
|
||||
input logic clk, reset,
|
||||
input logic [`XLEN-1:0] SATP_REGW, // includes SATP.MODE to determine number of levels in page table
|
||||
input logic [`XLEN-1:0] PCF, // addresses to translate
|
||||
input logic [`XLEN-1:0] PCFSpill, // addresses to translate
|
||||
input logic [`XLEN+1:0] IEUAdrExtM, // addresses to translate
|
||||
input logic [1:0] MemRWM, AtomicM,
|
||||
// system status
|
||||
@ -109,7 +109,7 @@ module hptw (
|
||||
assign TLBMiss = (DTLBMissOrDAFaultM | ITLBMissOrDAFaultF);
|
||||
|
||||
// Determine which address to translate
|
||||
mux2 #(`XLEN) vadrmux(PCF, IEUAdrExtM[`XLEN-1:0], DTLBWalk, TranslationVAdr);
|
||||
mux2 #(`XLEN) vadrmux(PCFSpill, IEUAdrExtM[`XLEN-1:0], DTLBWalk, TranslationVAdr);
|
||||
assign CurrentPPN = PTE[`PPN_BITS+9:10];
|
||||
|
||||
// State flops
|
||||
|
||||
@ -61,7 +61,9 @@ module csr #(parameter
|
||||
input logic BTBPredPCWrongM,
|
||||
input logic RASPredPCWrongM,
|
||||
input logic PredictionInstrClassWrongM,
|
||||
input logic BPPredWrongM, // branch predictor is wrong
|
||||
input logic [3:0] InstrClassM,
|
||||
input logic JumpOrTakenBranchM, // actual instruction class
|
||||
input logic DCacheMiss,
|
||||
input logic DCacheAccess,
|
||||
input logic ICacheMiss,
|
||||
@ -255,7 +257,7 @@ module csr #(parameter
|
||||
if (`ZICOUNTERS_SUPPORTED) begin:counters
|
||||
csrc counters(.clk, .reset, .StallE, .StallM, .FlushM,
|
||||
.InstrValidNotFlushedM, .LoadStallD, .CSRMWriteM,
|
||||
.DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM,
|
||||
.DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM, .JumpOrTakenBranchM, .BPPredWrongM,
|
||||
.InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
|
||||
.CSRAdrM, .PrivilegeModeW, .CSRWriteValM,
|
||||
.MCOUNTINHIBIT_REGW, .MCOUNTEREN_REGW, .SCOUNTEREN_REGW,
|
||||
|
||||
@ -48,7 +48,9 @@ module csrc #(parameter
|
||||
input logic BTBPredPCWrongM,
|
||||
input logic RASPredPCWrongM,
|
||||
input logic PredictionInstrClassWrongM,
|
||||
input logic BPPredWrongM, // branch predictor is wrong
|
||||
input logic [3:0] InstrClassM,
|
||||
input logic JumpOrTakenBranchM, // actual instruction class
|
||||
input logic DCacheMiss,
|
||||
input logic DCacheAccess,
|
||||
input logic ICacheMiss,
|
||||
@ -87,7 +89,7 @@ module csrc #(parameter
|
||||
assign CounterEvent[4] = DirPredictionWrongM & InstrValidNotFlushedM; // Branch predictor wrong direction
|
||||
assign CounterEvent[5] = InstrClassM[0] & InstrValidNotFlushedM; // branch instruction
|
||||
assign CounterEvent[6] = BTBPredPCWrongM & InstrValidNotFlushedM; // branch predictor wrong target
|
||||
assign CounterEvent[7] = (InstrClassM[3] | InstrClassM[1]) & InstrValidNotFlushedM; // jump instructions
|
||||
assign CounterEvent[7] = JumpOrTakenBranchM & InstrValidNotFlushedM; // jump or taken branch instructions
|
||||
assign CounterEvent[8] = RASPredPCWrongM & InstrValidNotFlushedM; // return address stack wrong address
|
||||
assign CounterEvent[9] = InstrClassM[2] & InstrValidNotFlushedM; // return instructions
|
||||
assign CounterEvent[10] = PredictionInstrClassWrongM & InstrValidNotFlushedM; // instruction class predictor wrong
|
||||
@ -95,7 +97,8 @@ module csrc #(parameter
|
||||
assign CounterEvent[12] = DCacheMiss; // data cache miss
|
||||
assign CounterEvent[13] = ICacheAccess; // instruction cache access
|
||||
assign CounterEvent[14] = ICacheMiss; // instruction cache miss
|
||||
assign CounterEvent[`COUNTERS-1:15] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
|
||||
assign CounterEvent[15] = BPPredWrongM & InstrValidNotFlushedM; // branch predictor wrong
|
||||
assign CounterEvent[`COUNTERS-1:16] = 0; // eventually give these sources, including FP instructions, I$/D$ misses, branches and mispredictions
|
||||
end
|
||||
|
||||
// Counter update and write logic
|
||||
|
||||
@ -46,11 +46,13 @@ module privileged (
|
||||
// processor events for performance counter logging
|
||||
input logic FRegWriteM, // instruction will write floating-point registers
|
||||
input logic LoadStallD, // load instruction is stalling
|
||||
input logic DirPredictionWrongM, // branch predictor guessed wrong directoin
|
||||
input logic BTBPredPCWrongM, // branch predictor guessed wrong target
|
||||
input logic RASPredPCWrongM, // return adddress stack guessed wrong target
|
||||
input logic PredictionInstrClassWrongM, // branch predictor guessed wrong instruction class
|
||||
input logic DirPredictionWrongM, // branch predictor guessed wrong directoin
|
||||
input logic BTBPredPCWrongM, // branch predictor guessed wrong target
|
||||
input logic RASPredPCWrongM, // return adddress stack guessed wrong target
|
||||
input logic PredictionInstrClassWrongM, // branch predictor guessed wrong instruction class
|
||||
input logic BPPredWrongM, // branch predictor is wrong
|
||||
input logic [3:0] InstrClassM, // actual instruction class
|
||||
input logic JumpOrTakenBranchM, // actual instruction class
|
||||
input logic DCacheMiss, // data cache miss
|
||||
input logic DCacheAccess, // data cache accessed (hit or miss)
|
||||
input logic ICacheMiss, // instruction cache miss
|
||||
@ -123,8 +125,8 @@ module privileged (
|
||||
.CSRReadM, .CSRWriteM, .TrapM, .mretM, .sretM, .wfiM, .IntPendingM, .InterruptM,
|
||||
.MTimerInt, .MExtInt, .SExtInt, .MSwInt,
|
||||
.MTIME_CLINT, .InstrValidM, .FRegWriteM, .LoadStallD,
|
||||
.DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM,
|
||||
.PredictionInstrClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess,
|
||||
.DirPredictionWrongM, .BTBPredPCWrongM, .RASPredPCWrongM, .BPPredWrongM,
|
||||
.PredictionInstrClassWrongM, .InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .JumpOrTakenBranchM,
|
||||
.NextPrivilegeModeM, .PrivilegeModeW, .CauseM, .SelHPTW,
|
||||
.STATUS_MPP, .STATUS_SPP, .STATUS_TSR, .STATUS_TVM,
|
||||
.STATUS_MIE, .STATUS_SIE, .STATUS_MXR, .STATUS_SUM, .STATUS_MPRV, .STATUS_TW, .STATUS_FS,
|
||||
|
||||
216
pipelined/src/wally/cvw.sv
Normal file
216
pipelined/src/wally/cvw.sv
Normal file
@ -0,0 +1,216 @@
|
||||
//////////////////////////////////////////
|
||||
// cvw.sv
|
||||
//
|
||||
// Written: David_Harris@hmc.edu 27 January 2022
|
||||
//
|
||||
// Purpose: package with shared CORE-V-Wally global parameters
|
||||
//
|
||||
// A component of the Wally configurable RISC-V project.
|
||||
//
|
||||
// Copyright (C) 2021 Harvey Mudd College & Oklahoma State University
|
||||
//
|
||||
// SPDX-License-Identifier: Apache-2.0 WITH SHL-2.1
|
||||
//
|
||||
// Licensed under the Solderpad Hardware License v 2.1 (the “License”); you may not use this file
|
||||
// except in compliance with the License, or, at your option, the Apache License version 2.0. You
|
||||
// may obtain a copy of the License at
|
||||
//
|
||||
// https://solderpad.org/licenses/SHL-2.1/
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, any work distributed under the
|
||||
// License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND,
|
||||
// either express or implied. See the License for the specific language governing permissions
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
// Usiing global `define statements isn't ideal in a large SystemVerilog system because
|
||||
// of the risk of `define name conflicts across different subsystems.
|
||||
// Instead, CORE-V-Wally loads the appropriate configuration one time and places it in a package
|
||||
// that is referenced by all Wally modules but not by other subsystems.
|
||||
|
||||
// Load configuration-specific information
|
||||
`include "wally-config.vh"
|
||||
|
||||
// Place configuration in a package
|
||||
package cvw;
|
||||
parameter XLEN = `XLEN;
|
||||
parameter FPGA = `FPGA;
|
||||
parameter QEMU = `QEMU;
|
||||
parameter IEEE754 = `IEEE754;
|
||||
parameter MISA = `MISA;
|
||||
parameter ZICSR_SUPPORTED = `ZICSR_SUPPORTED;
|
||||
parameter ZIFENCEI_SUPPORTED = `ZIFENCEI_SUPPORTED;
|
||||
parameter COUNTERS = `COUNTERS;
|
||||
parameter ZICOUNTERS_SUPPORTED = `ZICOUNTERS_SUPPORTED;
|
||||
parameter ZFH_SUPPORTED = `ZFH_SUPPORTED;
|
||||
parameter BUS_SUPPORTED = `BUS_SUPPORTED;
|
||||
parameter DCACHE_SUPPORTED = `DCACHE_SUPPORTED;
|
||||
parameter ICACHE_SUPPORTED = `ICACHE_SUPPORTED;
|
||||
parameter VIRTMEM_SUPPORTED = `VIRTMEM_SUPPORTED;
|
||||
parameter VECTORED_INTERRUPTS_SUPPORTED = `VECTORED_INTERRUPTS_SUPPORTED;
|
||||
parameter BIGENDIAN_SUPPORTED = `BIGENDIAN_SUPPORTED;
|
||||
parameter ITLB_ENTRIES = `ITLB_ENTRIES;
|
||||
parameter DTLB_ENTRIES = `DTLB_ENTRIES;
|
||||
parameter DCACHE_NUMWAYS = `DCACHE_NUMWAYS;
|
||||
parameter DCACHE_WAYSIZEINBYTES = `DCACHE_WAYSIZEINBYTES;
|
||||
parameter DCACHE_LINELENINBITS = `DCACHE_LINELENINBITS;
|
||||
parameter ICACHE_NUMWAYS = `ICACHE_NUMWAYS;
|
||||
parameter ICACHE_WAYSIZEINBYTES = `ICACHE_WAYSIZEINBYTES;
|
||||
parameter ICACHE_LINELENINBITS = `ICACHE_LINELENINBITS;
|
||||
parameter IDIV_BITSPERCYCLE = `IDIV_BITSPERCYCLE;
|
||||
parameter IDIV_ON_FPU = `IDIV_ON_FPU;
|
||||
parameter PMP_ENTRIES = `PMP_ENTRIES;
|
||||
parameter RESET_VECTOR = `RESET_VECTOR;
|
||||
parameter WFI_TIMEOUT_BIT = `WFI_TIMEOUT_BIT;
|
||||
parameter DTIM_SUPPORTED = `DTIM_SUPPORTED;
|
||||
parameter DTIM_BASE = `DTIM_BASE;
|
||||
parameter DTIM_RANGE = `DTIM_RANGE;
|
||||
parameter IROM_SUPPORTED = `IROM_SUPPORTED;
|
||||
parameter IROM_BASE = `IROM_BASE;
|
||||
parameter IROM_RANGE = `IROM_RANGE;
|
||||
parameter BOOTROM_SUPPORTED = `BOOTROM_SUPPORTED;
|
||||
parameter BOOTROM_BASE = `BOOTROM_BASE;
|
||||
parameter BOOTROM_RANGE = `BOOTROM_RANGE;
|
||||
parameter UNCORE_RAM_SUPPORTED = `UNCORE_RAM_SUPPORTED;
|
||||
parameter UNCORE_RAM_BASE = `UNCORE_RAM_BASE;
|
||||
parameter UNCORE_RAM_RANGE = `UNCORE_RAM_RANGE;
|
||||
parameter EXT_MEM_SUPPORTED = `EXT_MEM_SUPPORTED;
|
||||
parameter EXT_MEM_BASE = `EXT_MEM_BASE;
|
||||
parameter EXT_MEM_RANGE = `EXT_MEM_RANGE;
|
||||
parameter CLINT_SUPPORTED = `CLINT_SUPPORTED;
|
||||
parameter CLINT_BASE = `CLINT_BASE;
|
||||
parameter CLINT_RANGE = `CLINT_RANGE;
|
||||
parameter GPIO_SUPPORTED = `GPIO_SUPPORTED;
|
||||
parameter GPIO_BASE = `GPIO_BASE;
|
||||
parameter GPIO_RANGE = `GPIO_RANGE;
|
||||
parameter UART_SUPPORTED = `UART_SUPPORTED;
|
||||
parameter UART_BASE = `UART_BASE;
|
||||
parameter UART_RANGE = `UART_RANGE;
|
||||
parameter PLIC_SUPPORTED = `PLIC_SUPPORTED;
|
||||
parameter PLIC_BASE = `PLIC_BASE;
|
||||
parameter PLIC_RANGE = `PLIC_RANGE;
|
||||
parameter SDC_SUPPORTED = `SDC_SUPPORTED;
|
||||
parameter SDC_BASE = `SDC_BASE;
|
||||
parameter SDC_RANGE = `SDC_RANGE;
|
||||
parameter AHBW = `AHBW;
|
||||
parameter GPIO_LOOPBACK_TEST = `GPIO_LOOPBACK_TEST;
|
||||
parameter UART_PRESCALE = `UART_PRESCALE;
|
||||
parameter PLIC_NUM_SRC = `PLIC_NUM_SRC;
|
||||
parameter PLIC_GPIO_ID = `PLIC_GPIO_ID;
|
||||
parameter PLIC_UART_ID = `PLIC_UART_ID;
|
||||
parameter BPRED_SUPPORTED = `BPRED_SUPPORTED;
|
||||
parameter BPRED_TYPE = `BPRED_TYPE;
|
||||
parameter TESTSBP = `TESTSBP;
|
||||
parameter BPRED_SIZE = `BPRED_SIZE;
|
||||
parameter HPTW_WRITES_SUPPORTED = `HPTW_WRITES_SUPPORTED;
|
||||
// parameter = `;
|
||||
|
||||
|
||||
// Shared parameters
|
||||
|
||||
// constants defining different privilege modes
|
||||
// defined in Table 1.1 of the privileged spec
|
||||
parameter M_MODE = (2'b11);
|
||||
parameter S_MODE = (2'b01);
|
||||
parameter U_MODE = (2'b00);
|
||||
|
||||
// Virtual Memory Constants
|
||||
parameter VPN_SEGMENT_BITS = (`XLEN == 32 ? 10 : 9);
|
||||
parameter VPN_BITS = (`XLEN==32 ? (2*`VPN_SEGMENT_BITS) : (4*`VPN_SEGMENT_BITS));
|
||||
parameter PPN_BITS = (`XLEN==32 ? 22 : 44);
|
||||
parameter PA_BITS = (`XLEN==32 ? 34 : 56);
|
||||
parameter SVMODE_BITS = (`XLEN==32 ? 1 : 4);
|
||||
parameter ASID_BASE = (`XLEN==32 ? 22 : 44);
|
||||
parameter ASID_BITS = (`XLEN==32 ? 9 : 16);
|
||||
|
||||
// constants to check SATP_MODE against
|
||||
// defined in Table 4.3 of the privileged spec
|
||||
parameter NO_TRANSLATE = 0;
|
||||
parameter SV32 = 1;
|
||||
parameter SV39 = 8;
|
||||
parameter SV48 = 9;
|
||||
|
||||
// macros to define supported modes
|
||||
parameter A_SUPPORTED = ((`MISA >> 0) % 2 == 1);
|
||||
parameter B_SUPPORTED = ((`ZBA_SUPPORTED | `ZBB_SUPPORTED | `ZBC_SUPPORTED | `ZBS_SUPPORTED)); // not based on MISA
|
||||
parameter C_SUPPORTED = ((`MISA >> 2) % 2 == 1);
|
||||
parameter D_SUPPORTED = ((`MISA >> 3) % 2 == 1);
|
||||
parameter E_SUPPORTED = ((`MISA >> 4) % 2 == 1);
|
||||
parameter F_SUPPORTED = ((`MISA >> 5) % 2 == 1);
|
||||
parameter I_SUPPORTED = ((`MISA >> 8) % 2 == 1);
|
||||
parameter M_SUPPORTED = ((`MISA >> 12) % 2 == 1);
|
||||
parameter Q_SUPPORTED = ((`MISA >> 16) % 2 == 1);
|
||||
parameter S_SUPPORTED = ((`MISA >> 18) % 2 == 1);
|
||||
parameter U_SUPPORTED = ((`MISA >> 20) % 2 == 1);
|
||||
// N-mode user-level interrupts are depricated per Andrew Waterman 1/13/21
|
||||
|
||||
// logarithm of XLEN, used for number of index bits to select
|
||||
parameter LOG_XLEN = (`XLEN == 32 ? 5 : 6);
|
||||
|
||||
// Number of 64 bit PMP Configuration Register entries (or pairs of 32 bit entries)
|
||||
parameter PMPCFG_ENTRIES = (`PMP_ENTRIES/8);
|
||||
|
||||
// Floating point constants for Quad, Double, Single, and Half precisions
|
||||
parameter Q_LEN = 32'd128;
|
||||
parameter Q_NE = 32'd15;
|
||||
parameter Q_NF = 32'd112;
|
||||
parameter Q_BIAS = 32'd16383;
|
||||
parameter Q_FMT = 2'd3;
|
||||
parameter D_LEN = 32'd64;
|
||||
parameter D_NE = 32'd11;
|
||||
parameter D_NF = 32'd52;
|
||||
parameter D_BIAS = 32'd1023;
|
||||
parameter D_FMT = 2'd1;
|
||||
parameter S_LEN = 32'd32;
|
||||
parameter S_NE = 32'd8;
|
||||
parameter S_NF = 32'd23;
|
||||
parameter S_BIAS = 32'd127;
|
||||
parameter S_FMT = 2'd0;
|
||||
parameter H_LEN = 32'd16;
|
||||
parameter H_NE = 32'd5;
|
||||
parameter H_NF = 32'd10;
|
||||
parameter H_BIAS = 32'd15;
|
||||
parameter H_FMT = 2'd2;
|
||||
|
||||
// Floating point length FLEN and number of exponent (NE) and fraction (NF) bits
|
||||
parameter FLEN = (`Q_SUPPORTED ? `Q_LEN : `D_SUPPORTED ? `D_LEN : `S_LEN);
|
||||
parameter NE = (`Q_SUPPORTED ? `Q_NE : `D_SUPPORTED ? `D_NE : `S_NE);
|
||||
parameter NF = (`Q_SUPPORTED ? `Q_NF : `D_SUPPORTED ? `D_NF : `S_NF);
|
||||
parameter FMT = (`Q_SUPPORTED ? 2'd3 : `D_SUPPORTED ? 2'd1 : 2'd0);
|
||||
parameter BIAS = (`Q_SUPPORTED ? `Q_BIAS : `D_SUPPORTED ? `D_BIAS : `S_BIAS);
|
||||
|
||||
// Floating point constants needed for FPU paramerterization
|
||||
parameter FPSIZES = ((32)'(`Q_SUPPORTED)+(32)'(`D_SUPPORTED)+(32)'(`F_SUPPORTED)+(32)'(`ZFH_SUPPORTED));
|
||||
parameter FMTBITS = ((32)'(`FPSIZES>=3)+1);
|
||||
parameter LEN1 = ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_LEN : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_LEN : `H_LEN);
|
||||
parameter NE1 = ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NE : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NE : `H_NE);
|
||||
parameter NF1 = ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_NF : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_NF : `H_NF);
|
||||
parameter FMT1 = ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? 2'd1 : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? 2'd0 : 2'd2);
|
||||
parameter BIAS1 = ((`D_SUPPORTED & (`FLEN != `D_LEN)) ? `D_BIAS : (`F_SUPPORTED & (`FLEN != `S_LEN)) ? `S_BIAS : `H_BIAS);
|
||||
parameter LEN2 = ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_LEN : `H_LEN);
|
||||
parameter NE2 = ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NE : `H_NE);
|
||||
parameter NF2 = ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_NF : `H_NF);
|
||||
parameter FMT2 = ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? 2'd0 : 2'd2);
|
||||
parameter BIAS2 = ((`F_SUPPORTED & (`LEN1 != `S_LEN)) ? `S_BIAS : `H_BIAS);
|
||||
|
||||
// largest length in IEU/FPU
|
||||
parameter CVTLEN = ((`NF<`XLEN) ? (`XLEN) : (`NF));
|
||||
parameter LLEN = ((`FLEN<`XLEN) ? (`XLEN) : (`FLEN));
|
||||
parameter LOGCVTLEN = $unsigned($clog2(`CVTLEN+1));
|
||||
parameter NORMSHIFTSZ = (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVb + 1 +`NF+1) > (3*`NF+6) ? (`DIVb + 1 +`NF+1) : (3*`NF+6)));
|
||||
parameter LOGNORMSHIFTSZ = ($clog2(`NORMSHIFTSZ));
|
||||
parameter CORRSHIFTSZ = (((`CVTLEN+`NF+1)>(`DIVb + 1 +`NF+1) & (`CVTLEN+`NF+1)>(3*`NF+6)) ? (`CVTLEN+`NF+1) : ((`DIVN+1+`NF) > (3*`NF+4) ? (`DIVN+1+`NF) : (3*`NF+4)));
|
||||
|
||||
// division constants
|
||||
|
||||
parameter DIVN = (((`NF<`XLEN) & `IDIV_ON_FPU) ? `XLEN : `NF+2); // standard length of input
|
||||
parameter LOGR = ($clog2(`RADIX)); // r = log(R)
|
||||
parameter RK = (`LOGR*`DIVCOPIES); // r*k used for intdiv preproc
|
||||
parameter LOGRK = ($clog2(`RK)); // log2(r*k)
|
||||
parameter FPDUR = ((`DIVN+1+(`LOGR*`DIVCOPIES))/(`LOGR*`DIVCOPIES)+(`RADIX/4));
|
||||
parameter DURLEN = ($clog2(`FPDUR+1));
|
||||
parameter DIVb = (`FPDUR*`LOGR*`DIVCOPIES-1); // canonical fdiv size (b)
|
||||
parameter DIVBLEN = ($clog2(`DIVb+1)-1);
|
||||
parameter DIVa = (`DIVb+1-`XLEN); // used for idiv on fpu
|
||||
|
||||
endpackage
|
||||
@ -26,8 +26,7 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
/* verilator lint_on UNUSED */
|
||||
import cvw::*; // global CORE-V-Wally parameters
|
||||
|
||||
module wallypipelinedcore (
|
||||
input logic clk, reset,
|
||||
@ -35,12 +34,12 @@ module wallypipelinedcore (
|
||||
input logic MTimerInt, MExtInt, SExtInt, MSwInt,
|
||||
input logic [63:0] MTIME_CLINT,
|
||||
// Bus Interface
|
||||
input logic [`AHBW-1:0] HRDATA,
|
||||
input logic [AHBW-1:0] HRDATA,
|
||||
input logic HREADY, HRESP,
|
||||
output logic HCLK, HRESETn,
|
||||
output logic [`PA_BITS-1:0] HADDR,
|
||||
output logic [`AHBW-1:0] HWDATA,
|
||||
output logic [`XLEN/8-1:0] HWSTRB,
|
||||
output logic [PA_BITS-1:0] HADDR,
|
||||
output logic [AHBW-1:0] HWDATA,
|
||||
output logic [XLEN/8-1:0] HWSTRB,
|
||||
output logic HWRITE,
|
||||
output logic [2:0] HSIZE,
|
||||
output logic [2:0] HBURST,
|
||||
@ -58,15 +57,15 @@ module wallypipelinedcore (
|
||||
logic IntDivE, W64E;
|
||||
logic CSRReadM, CSRWriteM, PrivilegedM;
|
||||
logic [1:0] AtomicM;
|
||||
logic [`XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE;
|
||||
logic [`XLEN-1:0] SrcAM;
|
||||
logic [XLEN-1:0] ForwardedSrcAE, ForwardedSrcBE;
|
||||
logic [XLEN-1:0] SrcAM;
|
||||
logic [2:0] Funct3E;
|
||||
logic [31:0] InstrD;
|
||||
logic [31:0] InstrM;
|
||||
logic [`XLEN-1:0] PCF, PCE, PCLinkE;
|
||||
logic [`XLEN-1:0] PCM;
|
||||
logic [`XLEN-1:0] CSRReadValW, MDUResultW;
|
||||
logic [`XLEN-1:0] UnalignedPCNextF, PCNext2F;
|
||||
logic [XLEN-1:0] PCFSpill, PCE, PCLinkE;
|
||||
logic [XLEN-1:0] PCM;
|
||||
logic [XLEN-1:0] CSRReadValW, MDUResultW;
|
||||
logic [XLEN-1:0] UnalignedPCNextF, PCNext2F;
|
||||
logic [1:0] MemRWM;
|
||||
logic InstrValidM;
|
||||
logic InstrMisalignedFaultM;
|
||||
@ -86,9 +85,9 @@ module wallypipelinedcore (
|
||||
logic [4:0] RdE, RdM, RdW;
|
||||
logic FPUStallD;
|
||||
logic FWriteIntE;
|
||||
logic [`FLEN-1:0] FWriteDataM;
|
||||
logic [`XLEN-1:0] FIntResM;
|
||||
logic [`XLEN-1:0] FCvtIntResW;
|
||||
logic [FLEN-1:0] FWriteDataM;
|
||||
logic [XLEN-1:0] FIntResM;
|
||||
logic [XLEN-1:0] FCvtIntResW;
|
||||
logic FCvtIntW;
|
||||
logic FDivBusyE;
|
||||
logic IllegalFPUInstrM;
|
||||
@ -96,23 +95,23 @@ module wallypipelinedcore (
|
||||
logic FCvtIntStallD;
|
||||
logic FpLoadStoreM;
|
||||
logic [4:0] SetFflagsM;
|
||||
logic [`XLEN-1:0] FIntDivResultW;
|
||||
logic [XLEN-1:0] FIntDivResultW;
|
||||
|
||||
// memory management unit signals
|
||||
logic ITLBWriteF;
|
||||
logic ITLBMissF;
|
||||
logic [`XLEN-1:0] SATP_REGW;
|
||||
logic [XLEN-1:0] SATP_REGW;
|
||||
logic STATUS_MXR, STATUS_SUM, STATUS_MPRV;
|
||||
logic [1:0] STATUS_MPP, STATUS_FS;
|
||||
logic [1:0] PrivilegeModeW;
|
||||
logic [`XLEN-1:0] PTE;
|
||||
logic [XLEN-1:0] PTE;
|
||||
logic [1:0] PageType;
|
||||
logic sfencevmaM, WFIStallM;
|
||||
logic SelHPTW;
|
||||
|
||||
// PMA checker signals
|
||||
var logic [`XLEN-1:0] PMPADDR_ARRAY_REGW [`PMP_ENTRIES-1:0];
|
||||
var logic [7:0] PMPCFG_ARRAY_REGW[`PMP_ENTRIES-1:0];
|
||||
var logic [XLEN-1:0] PMPADDR_ARRAY_REGW[PMP_ENTRIES-1:0];
|
||||
var logic [7:0] PMPCFG_ARRAY_REGW[PMP_ENTRIES-1:0];
|
||||
|
||||
// IMem stalls
|
||||
logic IFUStallF;
|
||||
@ -120,14 +119,14 @@ module wallypipelinedcore (
|
||||
|
||||
// cpu lsu interface
|
||||
logic [2:0] Funct3M;
|
||||
logic [`XLEN-1:0] IEUAdrE;
|
||||
logic [`XLEN-1:0] WriteDataM;
|
||||
logic [`XLEN-1:0] IEUAdrM;
|
||||
logic [`LLEN-1:0] ReadDataW;
|
||||
logic [XLEN-1:0] IEUAdrE;
|
||||
logic [XLEN-1:0] WriteDataM;
|
||||
logic [XLEN-1:0] IEUAdrM;
|
||||
logic [LLEN-1:0] ReadDataW;
|
||||
logic CommittedM;
|
||||
|
||||
// AHB ifu interface
|
||||
logic [`PA_BITS-1:0] IFUHADDR;
|
||||
logic [PA_BITS-1:0] IFUHADDR;
|
||||
logic [2:0] IFUHBURST;
|
||||
logic [1:0] IFUHTRANS;
|
||||
logic [2:0] IFUHSIZE;
|
||||
@ -135,13 +134,13 @@ module wallypipelinedcore (
|
||||
logic IFUHREADY;
|
||||
|
||||
// AHB LSU interface
|
||||
logic [`PA_BITS-1:0] LSUHADDR;
|
||||
logic [`XLEN-1:0] LSUHWDATA;
|
||||
logic [`XLEN/8-1:0] LSUHWSTRB;
|
||||
logic [PA_BITS-1:0] LSUHADDR;
|
||||
logic [XLEN-1:0] LSUHWDATA;
|
||||
logic [XLEN/8-1:0] LSUHWSTRB;
|
||||
logic LSUHWRITE;
|
||||
logic LSUHREADY;
|
||||
|
||||
logic BPPredWrongE;
|
||||
logic BPPredWrongE, BPPredWrongM;
|
||||
logic DirPredictionWrongM;
|
||||
logic BTBPredPCWrongM;
|
||||
logic RASPredPCWrongM;
|
||||
@ -161,23 +160,20 @@ module wallypipelinedcore (
|
||||
logic BigEndianM;
|
||||
logic FCvtIntE;
|
||||
logic CommittedF;
|
||||
logic JumpOrTakenBranchM;
|
||||
|
||||
// Bit manipulation unit
|
||||
logic [`XLEN-1:0] BMUResultE; // Bit manipuation result BMU -> IEU
|
||||
logic BMUE; // is this a BMU instruction
|
||||
|
||||
// instruction fetch unit: PC, branch prediction, instruction cache
|
||||
ifu ifu(.clk, .reset,
|
||||
.StallF, .StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
|
||||
// Fetch
|
||||
.HRDATA, .PCF, .IFUHADDR, .PCNext2F,
|
||||
.HRDATA, .PCFSpill, .IFUHADDR, .PCNext2F,
|
||||
.IFUStallF, .IFUHBURST, .IFUHTRANS, .IFUHSIZE, .IFUHREADY, .IFUHWRITE,
|
||||
.ICacheAccess, .ICacheMiss,
|
||||
// Execute
|
||||
.PCLinkE, .PCSrcE, .IEUAdrE, .PCE, .BPPredWrongE,
|
||||
.PCLinkE, .PCSrcE, .IEUAdrE, .PCE, .BPPredWrongE, .BPPredWrongM,
|
||||
// Mem
|
||||
.CommittedF, .UnalignedPCNextF, .InvalidateICacheM, .CSRWriteFenceM,
|
||||
.InstrD, .InstrM, .PCM, .InstrClassM, .DirPredictionWrongM,
|
||||
.InstrD, .InstrM, .PCM, .InstrClassM, .DirPredictionWrongM, .JumpOrTakenBranchM,
|
||||
.BTBPredPCWrongM, .RASPredPCWrongM, .PredictionInstrClassWrongM,
|
||||
// Faults out
|
||||
.IllegalBaseInstrFaultD, .InstrPageFaultF, .IllegalIEUInstrFaultD, .InstrMisalignedFaultM,
|
||||
@ -193,7 +189,7 @@ module wallypipelinedcore (
|
||||
.InstrD, .IllegalIEUInstrFaultD, .IllegalBaseInstrFaultD,
|
||||
// Execute Stage interface
|
||||
.PCE, .PCLinkE, .FWriteIntE, .FCvtIntE, .IEUAdrE, .IntDivE, .W64E,
|
||||
.Funct3E, .ForwardedSrcAE, .ForwardedSrcBE, .BMUE,
|
||||
.Funct3E, .ForwardedSrcAE, .ForwardedSrcBE,
|
||||
// Memory stage interface
|
||||
.SquashSCW, // from LSU
|
||||
.MemRWM, // read/write control goes to LSU
|
||||
@ -203,7 +199,7 @@ module wallypipelinedcore (
|
||||
.SrcAM, // to privilege and fpu
|
||||
.RdE, .RdM, .FIntResM, .InvalidateICacheM, .FlushDCacheM,
|
||||
// Writeback stage
|
||||
.CSRReadValW, .MDUResultW, .BMUResultE, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[`XLEN-1:0]),
|
||||
.CSRReadValW, .MDUResultW, .FIntDivResultW, .RdW, .ReadDataW(ReadDataW[XLEN-1:0]),
|
||||
.InstrValidM, .FCvtIntResW, .FCvtIntW,
|
||||
// hazards
|
||||
.StallD, .StallE, .StallM, .StallW, .FlushD, .FlushE, .FlushM, .FlushW,
|
||||
@ -239,10 +235,10 @@ module wallypipelinedcore (
|
||||
.StoreAmoMisalignedFaultM, // connects to privilege
|
||||
.StoreAmoAccessFaultM, // connects to privilege
|
||||
.InstrDAPageFaultF,
|
||||
.PCF, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW,
|
||||
.PCFSpill, .ITLBMissF, .PTE, .PageType, .ITLBWriteF, .SelHPTW,
|
||||
.LSUStallM);
|
||||
|
||||
if(`BUS) begin : ebu
|
||||
if(BUS_SUPPORTED) begin : ebu
|
||||
ebu ebu(// IFU connections
|
||||
.clk, .reset,
|
||||
// IFU interface
|
||||
@ -280,7 +276,7 @@ module wallypipelinedcore (
|
||||
.FlushD, .FlushE, .FlushM, .FlushW);
|
||||
|
||||
// privileged unit
|
||||
if (`ZICSR_SUPPORTED) begin:priv
|
||||
if (ZICSR_SUPPORTED) begin:priv
|
||||
privileged priv(
|
||||
.clk, .reset,
|
||||
.FlushD, .FlushE, .FlushM, .FlushW, .StallD, .StallE, .StallM, .StallW,
|
||||
@ -289,9 +285,9 @@ module wallypipelinedcore (
|
||||
.RetM, .TrapM, .sfencevmaM,
|
||||
.InstrValidM, .CommittedM, .CommittedF,
|
||||
.FRegWriteM, .LoadStallD,
|
||||
.DirPredictionWrongM, .BTBPredPCWrongM,
|
||||
.DirPredictionWrongM, .BTBPredPCWrongM, .BPPredWrongM,
|
||||
.RASPredPCWrongM, .PredictionInstrClassWrongM,
|
||||
.InstrClassM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,
|
||||
.InstrClassM, .JumpOrTakenBranchM, .DCacheMiss, .DCacheAccess, .ICacheMiss, .ICacheAccess, .PrivilegedM,
|
||||
.InstrPageFaultF, .LoadPageFaultM, .StoreAmoPageFaultM,
|
||||
.InstrMisalignedFaultM, .IllegalIEUInstrFaultD,
|
||||
.LoadMisalignedFaultM, .StoreAmoMisalignedFaultM,
|
||||
@ -313,7 +309,7 @@ module wallypipelinedcore (
|
||||
end
|
||||
|
||||
// multiply/divide unit
|
||||
if (`M_SUPPORTED) begin:mdu
|
||||
if (M_SUPPORTED) begin:mdu
|
||||
mdu mdu(.clk, .reset, .StallM, .StallW, .FlushE, .FlushM, .FlushW,
|
||||
.ForwardedSrcAE, .ForwardedSrcBE,
|
||||
.Funct3E, .Funct3M, .IntDivE, .W64E,
|
||||
@ -324,12 +320,12 @@ module wallypipelinedcore (
|
||||
end
|
||||
|
||||
// floating point unit
|
||||
if (`F_SUPPORTED) begin:fpu
|
||||
if (F_SUPPORTED) begin:fpu
|
||||
fpu fpu(
|
||||
.clk, .reset,
|
||||
.FRM_REGW, // Rounding mode from CSR
|
||||
.InstrD, // instruction from IFU
|
||||
.ReadDataW(ReadDataW[`FLEN-1:0]),// Read data from memory
|
||||
.ReadDataW(ReadDataW[FLEN-1:0]),// Read data from memory
|
||||
.ForwardedSrcAE, // Integer input being processed (from IEU)
|
||||
.StallE, .StallM, .StallW, // stall signals from HZU
|
||||
.FlushE, .FlushM, .FlushW, // flush signals from HZU
|
||||
@ -360,15 +356,5 @@ module wallypipelinedcore (
|
||||
assign SetFflagsM = 0;
|
||||
assign FpLoadStoreM = 0;
|
||||
end
|
||||
|
||||
// bit manipulation unit
|
||||
if (`B_SUPPORTED) begin:bmu
|
||||
bmu bmu(.ForwardedSrcAE, .ForwardedSrcBE, .InstrD, .BMUE, .BMUResultE);
|
||||
end else begin // no B instructions supported
|
||||
assign BMUResultE = 0;
|
||||
assign BMUE = 0;
|
||||
end
|
||||
|
||||
|
||||
|
||||
endmodule
|
||||
|
||||
@ -26,21 +26,21 @@
|
||||
// and limitations under the License.
|
||||
////////////////////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
`include "wally-config.vh"
|
||||
import cvw::*; // global CORE-V-Wally parameters
|
||||
|
||||
module wallypipelinedsoc (
|
||||
input logic clk,
|
||||
input logic reset_ext, // external asynchronous reset pin
|
||||
output logic reset, // reset synchronized to clk to prevent races on release
|
||||
// AHB Interface
|
||||
input logic [`AHBW-1:0] HRDATAEXT,
|
||||
input logic [AHBW-1:0] HRDATAEXT,
|
||||
input logic HREADYEXT, HRESPEXT,
|
||||
output logic HSELEXT,
|
||||
// outputs to external memory, shared with uncore memory
|
||||
output logic HCLK, HRESETn,
|
||||
output logic [`PA_BITS-1:0] HADDR,
|
||||
output logic [`AHBW-1:0] HWDATA,
|
||||
output logic [`XLEN/8-1:0] HWSTRB,
|
||||
output logic [PA_BITS-1:0] HADDR,
|
||||
output logic [AHBW-1:0] HWDATA,
|
||||
output logic [XLEN/8-1:0] HWSTRB,
|
||||
output logic HWRITE,
|
||||
output logic [2:0] HSIZE,
|
||||
output logic [2:0] HBURST,
|
||||
@ -63,7 +63,7 @@ module wallypipelinedsoc (
|
||||
);
|
||||
|
||||
// Uncore signals
|
||||
logic [`AHBW-1:0] HRDATA; // from AHB mux in uncore
|
||||
logic [AHBW-1:0] HRDATA; // from AHB mux in uncore
|
||||
logic HRESP; // response from AHB
|
||||
logic MTimerInt, MSwInt; // timer and software interrupts from CLINT
|
||||
logic [63:0] MTIME_CLINT; // from CLINT to CSRs
|
||||
@ -80,7 +80,7 @@ module wallypipelinedsoc (
|
||||
);
|
||||
|
||||
// instantiate uncore if a bus interface exists
|
||||
if (`BUS) begin : uncore
|
||||
if (BUS_SUPPORTED) begin : uncore
|
||||
uncore uncore(.HCLK, .HRESETn, .TIMECLK,
|
||||
.HADDR, .HWDATA, .HWSTRB, .HWRITE, .HSIZE, .HBURST, .HPROT, .HTRANS, .HMASTLOCK, .HRDATAEXT,
|
||||
.HREADYEXT, .HRESPEXT, .HRDATA, .HREADY, .HRESP, .HSELEXT,
|
||||
|
||||
@ -48,7 +48,7 @@ module FunctionName(reset, clk, ProgramAddrMapFile, ProgramLabelMapFile);
|
||||
logic StallD, StallE, FlushD, FlushE;
|
||||
integer ProgramAddrIndex, ProgramAddrIndexQ;
|
||||
|
||||
assign PCF = testbench.dut.core.PCF;
|
||||
assign PCF = testbench.dut.core.ifu.PCF;
|
||||
assign StallD = testbench.dut.core.StallD;
|
||||
assign StallE = testbench.dut.core.StallE;
|
||||
assign FlushD = testbench.dut.core.FlushD;
|
||||
|
||||
@ -32,7 +32,7 @@
|
||||
module sd_top_tb();
|
||||
|
||||
|
||||
localparam integer g_COUNT_WIDTH = 8;
|
||||
localparam g_COUNT_WIDTH = 8;
|
||||
|
||||
logic a_RST;
|
||||
logic i_SD_CMD;
|
||||
|
||||
@ -205,8 +205,8 @@ logic [3:0] dummy;
|
||||
InstrFName, InstrDName, InstrEName, InstrMName, InstrWName);
|
||||
|
||||
// initialize tests
|
||||
localparam integer MemStartAddr = 0;
|
||||
localparam integer MemEndAddr = `UNCORE_RAM_RANGE>>1+(`XLEN/32);
|
||||
localparam MemStartAddr = 0;
|
||||
localparam MemEndAddr = `UNCORE_RAM_RANGE>>1+(`XLEN/32);
|
||||
|
||||
initial
|
||||
begin
|
||||
@ -246,7 +246,7 @@ logic [3:0] dummy;
|
||||
force dut.uncore.uncore.sdc.SDC.LimitTimers = 1;
|
||||
end else begin
|
||||
if (`IROM_SUPPORTED) $readmemh(memfilename, dut.core.ifu.irom.irom.rom.ROM);
|
||||
else if (`BUS) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
|
||||
else if (`BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
|
||||
if (`DTIM_SUPPORTED) $readmemh(memfilename, dut.core.lsu.dtim.dtim.ram.RAM);
|
||||
end
|
||||
|
||||
@ -408,7 +408,7 @@ logic [3:0] dummy;
|
||||
end // always @ (negedge clk)
|
||||
|
||||
|
||||
if(`PrintHPMCounters) begin
|
||||
if(`PrintHPMCounters & `ZICOUNTERS_SUPPORTED) begin
|
||||
integer HPMCindex;
|
||||
string HPMCnames[] = '{"Mcycle",
|
||||
"------",
|
||||
@ -424,7 +424,8 @@ logic [3:0] dummy;
|
||||
"D Cache Access",
|
||||
"D Cache Miss",
|
||||
"I Cache Access",
|
||||
"I Cache Miss"};
|
||||
"I Cache Miss",
|
||||
"Br Pred Wrong"};
|
||||
always @(negedge clk) begin
|
||||
if(DCacheFlushStart & ~DCacheFlushDone) begin
|
||||
for(HPMCindex = 0; HPMCindex < HPMCnames.size(); HPMCindex += 1) begin
|
||||
@ -465,7 +466,7 @@ logic [3:0] dummy;
|
||||
.done(DCacheFlushDone));
|
||||
|
||||
// initialize the branch predictor
|
||||
if (`BPRED_ENABLED == 1)
|
||||
if (`BPRED_SUPPORTED == 1)
|
||||
begin
|
||||
genvar adrindex;
|
||||
|
||||
@ -483,11 +484,13 @@ logic [3:0] dummy;
|
||||
if (`BPRED_LOGGER) begin
|
||||
string direction;
|
||||
int file;
|
||||
logic PCSrcM;
|
||||
flopenrc #(1) PCSrcMReg(clk, reset, dut.core.FlushM, ~dut.core.StallM, dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcE, PCSrcM);
|
||||
initial
|
||||
file = $fopen("branch.log", "w");
|
||||
always @(posedge clk) begin
|
||||
if(dut.core.ifu.InstrClassM[0] & ~dut.core.StallW & ~dut.core.FlushW & dut.core.InstrValidM) begin
|
||||
direction = dut.core.ifu.bpred.bpred.Predictor.DirPredictor.PCSrcM ? "t" : "n";
|
||||
direction = PCSrcM ? "t" : "n";
|
||||
$fwrite(file, "%h %s\n", dut.core.PCM, direction);
|
||||
end
|
||||
end
|
||||
@ -523,19 +526,19 @@ module riscvassertions;
|
||||
assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double fp (D) without supporting float (F)");
|
||||
assert (`D_SUPPORTED | ~`Q_SUPPORTED) else $error("Can't support quad fp (Q) without supporting double (D)");
|
||||
assert (`F_SUPPORTED | ~`ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)");
|
||||
assert (`DCACHE | ~`F_SUPPORTED | `FLEN <= `XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN");
|
||||
assert (`DCACHE_SUPPORTED | ~`F_SUPPORTED | `FLEN <= `XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN");
|
||||
assert (`I_SUPPORTED ^ `E_SUPPORTED) else $error("Exactly one of I and E must be supported");
|
||||
assert (`FLEN<=`XLEN | `DCACHE | `DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported");
|
||||
assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (!`DCACHE) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||
assert (`DCACHE_LINELENINBITS >= 128 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
|
||||
assert (`FLEN<=`XLEN | `DCACHE_SUPPORTED | `DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported");
|
||||
assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (!`DCACHE_SUPPORTED) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||
assert (`DCACHE_LINELENINBITS >= 128 | (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
|
||||
assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size");
|
||||
assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (!`ICACHE) | `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||
assert (`ICACHE_LINELENINBITS >= 32 | (!`ICACHE)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
|
||||
assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (!`ICACHE_SUPPORTED) | `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||
assert (`ICACHE_LINELENINBITS >= 32 | (!`ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
|
||||
assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size");
|
||||
assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must be a power of 2");
|
||||
assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | (!`DCACHE)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
|
||||
assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS | (!`ICACHE)) else $error("ICACHE_LINELENINBITS must be a power of 2");
|
||||
assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | (!`ICACHE)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
|
||||
assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be a power of 2");
|
||||
assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | (!`DCACHE_SUPPORTED)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
|
||||
assert (2**$clog2(`ICACHE_LINELENINBITS) == `ICACHE_LINELENINBITS | (!`ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be a power of 2");
|
||||
assert (2**$clog2(`ICACHE_WAYSIZEINBYTES) == `ICACHE_WAYSIZEINBYTES | (!`ICACHE_SUPPORTED)) else $error("ICACHE_WAYSIZEINBYTES must be a power of 2");
|
||||
assert (2**$clog2(`ITLB_ENTRIES) == `ITLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("ITLB_ENTRIES must be a power of 2");
|
||||
assert (2**$clog2(`DTLB_ENTRIES) == `DTLB_ENTRIES | `VIRTMEM_SUPPORTED==0) else $error("DTLB_ENTRIES must be a power of 2");
|
||||
assert (`UNCORE_RAM_RANGE >= 56'h07FFFFFF) else $warning("Some regression tests will fail if UNCORE_RAM_RANGE is less than 56'h07FFFFFF");
|
||||
@ -543,12 +546,12 @@ module riscvassertions;
|
||||
assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZISR not supported");
|
||||
assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported");
|
||||
assert (`VIRTMEM_SUPPORTED == 0 | (`DTIM_SUPPORTED == 0 & `IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses");
|
||||
assert (`DCACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache");
|
||||
assert (`ICACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache");
|
||||
assert ((`DCACHE == 0 & `ICACHE == 0) | `BUS) else $error("Dcache and Icache requires DBUS.");
|
||||
assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1");
|
||||
assert (`DCACHE_SUPPORTED | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache");
|
||||
assert (`ICACHE_SUPPORTED | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache");
|
||||
assert ((`DCACHE_SUPPORTED == 0 & `ICACHE_SUPPORTED == 0) | `BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS_SUPPORTED.");
|
||||
assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE_SUPPORTED)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1");
|
||||
assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words");
|
||||
assert (`DCACHE | `A_SUPPORTED == 0) else $error("Atomic extension (A) requires cache on Wally.");
|
||||
assert (`DCACHE_SUPPORTED | `A_SUPPORTED == 0) else $error("Atomic extension (A) requires cache on Wally.");
|
||||
assert (`IDIV_ON_FPU == 0 | `F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED");
|
||||
end
|
||||
|
||||
@ -569,26 +572,24 @@ module DCacheFlushFSM
|
||||
|
||||
logic [`XLEN-1:0] ShadowRAM[`UNCORE_RAM_BASE>>(1+`XLEN/32):(`UNCORE_RAM_RANGE+`UNCORE_RAM_BASE)>>1+(`XLEN/32)];
|
||||
|
||||
if(`DCACHE) begin
|
||||
localparam integer numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES;
|
||||
localparam integer numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS;
|
||||
localparam integer linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN;
|
||||
localparam integer linelen = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN;
|
||||
localparam integer sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN;
|
||||
localparam integer cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM;
|
||||
|
||||
//testbench.dut.core.lsu.bus.dcache.dcache.CacheWays.NUMSRAM;
|
||||
localparam integer numwords = sramlen/`XLEN;
|
||||
localparam integer lognumlines = $clog2(numlines);
|
||||
localparam integer loglinebytelen = $clog2(linebytelen);
|
||||
localparam integer lognumways = $clog2(numways);
|
||||
localparam integer tagstart = lognumlines + loglinebytelen;
|
||||
if(`DCACHE_SUPPORTED) begin
|
||||
localparam numlines = testbench.dut.core.lsu.bus.dcache.dcache.NUMLINES;
|
||||
localparam numways = testbench.dut.core.lsu.bus.dcache.dcache.NUMWAYS;
|
||||
localparam linebytelen = testbench.dut.core.lsu.bus.dcache.dcache.LINEBYTELEN;
|
||||
localparam linelen = testbench.dut.core.lsu.bus.dcache.dcache.LINELEN;
|
||||
localparam sramlen = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].SRAMLEN;
|
||||
localparam cachesramwords = testbench.dut.core.lsu.bus.dcache.dcache.CacheWays[0].NUMSRAM;
|
||||
localparam numwords = sramlen/`XLEN;
|
||||
localparam lognumlines = $clog2(numlines);
|
||||
localparam loglinebytelen = $clog2(linebytelen);
|
||||
localparam lognumways = $clog2(numways);
|
||||
localparam tagstart = lognumlines + loglinebytelen;
|
||||
|
||||
|
||||
|
||||
genvar index, way, cacheWord;
|
||||
logic [sramlen-1:0] CacheData [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
|
||||
logic [sramlen-1:0] cacheline;
|
||||
logic [sramlen-1:0] cacheline;
|
||||
logic [`XLEN-1:0] CacheTag [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
|
||||
logic CacheValid [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
|
||||
logic CacheDirty [numways-1:0] [numlines-1:0] [cachesramwords-1:0];
|
||||
|
||||
@ -100,8 +100,8 @@ module testbench;
|
||||
pathname = "../../tests/riscof/work/wally-riscv-arch-test/";
|
||||
|
||||
memfilename = {pathname, testName, "/ref/ref.elf.memfile"};
|
||||
if (`BUS) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
|
||||
else $error("Imperas test bench requires BUS.");
|
||||
if (`BUS_SUPPORTED) $readmemh(memfilename, dut.uncore.uncore.ram.ram.memory.RAM);
|
||||
else $error("Imperas test bench requires BUS_SUPPORTED.");
|
||||
|
||||
ProgramAddrMapFile = {pathname, testName, "/ref/ref.elf.objdump.addr"};
|
||||
ProgramLabelMapFile = {pathname, testName, "/ref/ref.elf.objdump.lab"};
|
||||
@ -219,7 +219,7 @@ module testbench;
|
||||
.done(DCacheFlushDone));
|
||||
|
||||
// initialize the branch predictor
|
||||
if (`BPRED_ENABLED == 1)
|
||||
if (`BPRED_SUPPORTED == 1)
|
||||
begin
|
||||
genvar adrindex;
|
||||
|
||||
@ -265,14 +265,14 @@ module riscvassertions;
|
||||
assert (`F_SUPPORTED | ~`D_SUPPORTED) else $error("Can't support double fp (D) without supporting float (F)");
|
||||
assert (`D_SUPPORTED | ~`Q_SUPPORTED) else $error("Can't support quad fp (Q) without supporting double (D)");
|
||||
assert (`F_SUPPORTED | ~`ZFH_SUPPORTED) else $error("Can't support half-precision fp (ZFH) without supporting float (F)");
|
||||
assert (`DCACHE | ~`F_SUPPORTED | `FLEN <= `XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN");
|
||||
assert (`DCACHE_SUPPORTED | ~`F_SUPPORTED | `FLEN <= `XLEN) else $error("Data cache required to support FLEN > XLEN because AHB bus width is XLEN");
|
||||
assert (`I_SUPPORTED ^ `E_SUPPORTED) else $error("Exactly one of I and E must be supported");
|
||||
assert (`FLEN<=`XLEN | `DCACHE | `DTIM_SUPPORTED) else $error("Wally does not support FLEN > XLEN unleses data cache or DTIM is supported");
|
||||
assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (!`DCACHE) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||
assert (`DCACHE_LINELENINBITS >= 128 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
|
||||
assert (`DCACHE_WAYSIZEINBYTES <= 4096 | (!`DCACHE_SUPPORTED) | `VIRTMEM_SUPPORTED == 0) else $error("DCACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||
assert (`DCACHE_LINELENINBITS >= 128 | (!`DCACH_SUPPORTED)) else $error("DCACHE_LINELENINBITS must be at least 128 when caches are enabled");
|
||||
assert (`DCACHE_LINELENINBITS < `DCACHE_WAYSIZEINBYTES*8) else $error("DCACHE_LINELENINBITS must be smaller than way size");
|
||||
assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (!`ICACHE) | `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||
assert (`ICACHE_LINELENINBITS >= 32 | (!`ICACHE)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
|
||||
assert (`ICACHE_WAYSIZEINBYTES <= 4096 | (!`ICACHE_SUPPORTED) | `VIRTMEM_SUPPORTED == 0) else $error("ICACHE_WAYSIZEINBYTES cannot exceed 4 KiB when caches and vitual memory is enabled (to prevent aliasing)");
|
||||
assert (`ICACHE_LINELENINBITS >= 32 | (!`ICACHE_SUPPORTED)) else $error("ICACHE_LINELENINBITS must be at least 32 when caches are enabled");
|
||||
assert (`ICACHE_LINELENINBITS < `ICACHE_WAYSIZEINBYTES*8) else $error("ICACHE_LINELENINBITS must be smaller than way size");
|
||||
assert (2**$clog2(`DCACHE_LINELENINBITS) == `DCACHE_LINELENINBITS | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must be a power of 2");
|
||||
assert (2**$clog2(`DCACHE_WAYSIZEINBYTES) == `DCACHE_WAYSIZEINBYTES | (!`DCACHE)) else $error("DCACHE_WAYSIZEINBYTES must be a power of 2");
|
||||
@ -285,12 +285,12 @@ module riscvassertions;
|
||||
assert (`ZICSR_SUPPORTED == 1 | (`S_SUPPORTED == 0 & `U_SUPPORTED == 0)) else $error("S and U modes not supported if ZISR not supported");
|
||||
assert (`U_SUPPORTED | (`S_SUPPORTED == 0)) else $error ("S mode only supported if U also is supported");
|
||||
assert (`VIRTMEM_SUPPORTED == 0 | (`DTIM_SUPPORTED == 0 & `IROM_SUPPORTED == 0)) else $error("Can't simultaneously have virtual memory and DTIM_SUPPORTED/IROM_SUPPORTED because local memories don't translate addresses");
|
||||
assert (`DCACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache");
|
||||
assert (`ICACHE | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache");
|
||||
assert ((`DCACHE == 0 & `ICACHE == 0) | `BUS) else $error("Dcache and Icache requires DBUS.");
|
||||
assert (`DCACHE_SUPPORTED | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs dcache");
|
||||
assert (`ICACHE_SUPPORTED | `VIRTMEM_SUPPORTED ==0) else $error("Virtual memory needs icache");
|
||||
assert ((`DCACHE_SUPPORTED == 0 & `ICACHE_SUPPORTED == 0) | `BUS_SUPPORTED) else $error("Dcache and Icache requires DBUS.");
|
||||
assert (`DCACHE_LINELENINBITS <= `XLEN*16 | (!`DCACHE)) else $error("DCACHE_LINELENINBITS must not exceed 16 words because max AHB burst size is 1");
|
||||
assert (`DCACHE_LINELENINBITS % 4 == 0) else $error("DCACHE_LINELENINBITS must hold 4, 8, or 16 words");
|
||||
assert (`DCACHE | `A_SUPPORTED == 0) else $error("Atomic extension (A) requires cache on Wally.");
|
||||
assert (`DCACHE_SUPPORTED | `A_SUPPORTED == 0) else $error("Atomic extension (A) requires cache on Wally.");
|
||||
assert (`IDIV_ON_FPU == 0 | `F_SUPPORTED) else $error("IDIV on FPU needs F_SUPPORTED");
|
||||
end
|
||||
|
||||
|
||||
@ -24,6 +24,7 @@ export DRIVE ?= FLOP
|
||||
time := $(shell date +%F-%H-%M)
|
||||
hash := $(shell git rev-parse --short HEAD)
|
||||
export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash)
|
||||
export OUTPUTDIR := runs/$(DESIGN)_$(CONFIG)_$(MOD)_$(TECH)nm_$(FREQ)_MHz_$(time)_$(TITLE)_$(hash)
|
||||
export SAIFPOWER ?= 0
|
||||
|
||||
OLDCONFIGDIR ?= ${WALLY}/pipelined/config
|
||||
@ -43,6 +44,8 @@ default:
|
||||
@echo "Use wallySynth.py to run a concurrent sweep "
|
||||
|
||||
|
||||
DIRS32 = rv32e rv32gc rv32ic rv32i
|
||||
DIRS64 = rv64i rv64gc
|
||||
DIRS32 = rv32e rv32gc rv32ic rv32i
|
||||
DIRS64 = rv64i rv64gc
|
||||
DIRS = $(DIRS32) $(DIRS64)
|
||||
@ -96,22 +99,35 @@ ifeq ($(SAIFPOWER), 1)
|
||||
cp -f ../pipelined/regression/power.saif .
|
||||
endif
|
||||
|
||||
ifeq ($(SAIFPOWER), 1)
|
||||
cp -f ../pipelined/regression/power.saif .
|
||||
endif
|
||||
|
||||
freqs:
|
||||
@$(foreach freq, $(FREQS), make synth DESIGN=wallypipelinedcore CONFIG=rv32e FREQ=$(freq) MAXCORES=1;)
|
||||
|
||||
mkdirecs:
|
||||
mkdirecs:
|
||||
@echo "DC Synthesis"
|
||||
@mkdir -p $(OUTPUTDIR)
|
||||
@mkdir -p $(OUTPUTDIR)/hdl/config
|
||||
@mkdir -p $(OUTPUTDIR)/hdl/config
|
||||
@mkdir -p $(OUTPUTDIR)/reports
|
||||
@mkdir -p $(OUTPUTDIR)/mapped
|
||||
@mkdir -p $(OUTPUTDIR)/unmapped
|
||||
|
||||
synth: mkdirecs configs rundc clean
|
||||
|
||||
rundc:
|
||||
|
||||
synth: mkdirecs configs rundc clean
|
||||
|
||||
rundc:
|
||||
dc_shell-xg-t -64bit -f scripts/$(NAME).tcl | tee $(OUTPUTDIR)/$(NAME).out
|
||||
|
||||
clean:
|
||||
rm -rf $(OUTPUTDIR)/hdl
|
||||
|
||||
clean:
|
||||
rm -rf $(OUTPUTDIR)/hdl
|
||||
rm -rf $(OUTPUTDIR)/WORK
|
||||
|
||||
@ -16,7 +16,7 @@ root:
|
||||
mkdir -p $(work)
|
||||
mkdir -p $(arch_workdir)
|
||||
mkdir -p $(wally_workdir)
|
||||
sed 's,{0},$(current_dir),g;s,{1},32imc,g' config.ini > config32.ini
|
||||
sed 's,{0},$(current_dir),g;s,{1},32gc,g' config.ini > config32.ini
|
||||
sed 's,{0},$(current_dir),g;s,{1},64gc,g' config.ini > config64.ini
|
||||
sed 's,{0},$(current_dir),g;s,{1},32e,g' config.ini > config32e.ini
|
||||
|
||||
|
||||
@ -1,11 +1,11 @@
|
||||
hart_ids: [0]
|
||||
hart0:
|
||||
ISA: RV32EMFCZicsr_Zifencei
|
||||
ISA: RV32EMCZicsr_Zifencei
|
||||
physical_addr_sz: 32
|
||||
User_Spec_Version: '2.3'
|
||||
supported_xlen: [32]
|
||||
misa:
|
||||
reset-val: 0x40001034
|
||||
reset-val: 0x40001014
|
||||
rv32:
|
||||
accessible: true
|
||||
mxl:
|
||||
|
||||
@ -76,11 +76,6 @@ def writeVector(a, b, storecmd, xlen):
|
||||
lines = lines + storecmd + " x" + str(reg3) + ", " + str(wordsize*testnum) + "(x6)\n"
|
||||
# lines = lines + "RVTEST_IO_ASSERT_GPR_EQ(x7, " + str(reg3) +", "+formatstr.format(expected)+")\n"
|
||||
f.write(lines)
|
||||
if (xlen == 32):
|
||||
line = formatrefstr.format(expected)+"\n"
|
||||
else:
|
||||
line = formatrefstr.format(expected % 2**32)+"\n" + formatrefstr.format(expected >> 32) + "\n"
|
||||
r.write(line)
|
||||
testnum = testnum+1
|
||||
|
||||
##################################
|
||||
@ -114,12 +109,10 @@ for xlen in xlens:
|
||||
pathname = "../wally-riscv-arch-test/riscv-test-suite/rv" + str(xlen) + "i_m/I/"
|
||||
basename = "WALLY-" + test
|
||||
fname = pathname + "src/" + basename + ".S"
|
||||
refname = pathname + "references/" + basename + ".reference_output"
|
||||
testnum = 0
|
||||
|
||||
# print custom header part
|
||||
f = open(fname, "w")
|
||||
r = open(refname, "w")
|
||||
line = "///////////////////////////////////////////\n"
|
||||
f.write(line)
|
||||
lines="// "+fname+ "\n// " + author + "\n"
|
||||
@ -154,7 +147,6 @@ for xlen in xlens:
|
||||
# lines = lines + "\nRV_COMPLIANCE_DATA_END\n"
|
||||
f.write(lines)
|
||||
f.close()
|
||||
r.close()
|
||||
|
||||
|
||||
|
||||
|
||||
@ -1,580 +0,0 @@
|
||||
bfffffff
|
||||
00004000
|
||||
bfffdffe
|
||||
e000003f
|
||||
56666665
|
||||
f7fffffa
|
||||
fbff4afc
|
||||
ffffffff
|
||||
00000000
|
||||
ef7ffffe
|
||||
ffc0ffff
|
||||
1fdfffff
|
||||
fff00002
|
||||
fff74afc
|
||||
003bffff
|
||||
fffe001f
|
||||
ffff0005
|
||||
3332b333
|
||||
3fffbfff
|
||||
fbffdffe
|
||||
fffeeffe
|
||||
0001f7ff
|
||||
66666265
|
||||
dffffdfe
|
||||
ffffff07
|
||||
ffffff3e
|
||||
7fffffbe
|
||||
66666646
|
||||
55555545
|
||||
fffffff9
|
||||
ffff7ffa
|
||||
0ffffffd
|
||||
66666665
|
||||
dfffffff
|
||||
5e666665
|
||||
fdff4afc
|
||||
ff0fffff
|
||||
bf7fffff
|
||||
00bfffff
|
||||
55355555
|
||||
002fffff
|
||||
ffffffff
|
||||
007bffff
|
||||
bffdffff
|
||||
003fbfff
|
||||
fffff03f
|
||||
1ffff7ff
|
||||
ffff7bfe
|
||||
ffffddfe
|
||||
ffffff03
|
||||
333332b1
|
||||
0000001f
|
||||
efffffee
|
||||
01fffff7
|
||||
55555552
|
||||
1ffffffe
|
||||
80000004
|
||||
3ffffffa
|
||||
0ffffff8
|
||||
07fffffa
|
||||
03fffffb
|
||||
55755556
|
||||
00040002
|
||||
00020020
|
||||
0000fdff
|
||||
fe007fff
|
||||
00002fff
|
||||
ffff9fff
|
||||
ffff5afc
|
||||
fc0007ff
|
||||
00001400
|
||||
aaaaacaa
|
||||
00040100
|
||||
fc00007f
|
||||
0000000f
|
||||
00000110
|
||||
0000000a
|
||||
00010002
|
||||
00000005
|
||||
07fffff6
|
||||
03dfffff
|
||||
00fffffc
|
||||
00800000
|
||||
66866666
|
||||
55655556
|
||||
00080200
|
||||
aaab2aab
|
||||
00004100
|
||||
00008800
|
||||
01000400
|
||||
00040200
|
||||
0000b585
|
||||
0000b514
|
||||
ffffff80
|
||||
00016a0a
|
||||
00000002
|
||||
66671b6c
|
||||
3333e839
|
||||
0000b50b
|
||||
aaab5fb0
|
||||
55560a5b
|
||||
0000b509
|
||||
00016a08
|
||||
0000b505
|
||||
66671b6a
|
||||
3333e837
|
||||
55560a59
|
||||
0000b507
|
||||
00016a09
|
||||
00000001
|
||||
66671b6b
|
||||
3333e838
|
||||
0000b50a
|
||||
aaab5faf
|
||||
55560a5a
|
||||
0000b508
|
||||
00000002
|
||||
fffe95fa
|
||||
6665b164
|
||||
33327e31
|
||||
ffff4b03
|
||||
aaa9f5a8
|
||||
5554a053
|
||||
ffff4b01
|
||||
00000000
|
||||
ffff4afd
|
||||
6665b162
|
||||
33327e2f
|
||||
5554a051
|
||||
ffff4aff
|
||||
00000001
|
||||
fffe95f9
|
||||
6665b163
|
||||
33327e30
|
||||
ffff4b02
|
||||
aaa9f5a7
|
||||
5554a052
|
||||
ffff4b00
|
||||
66671b6c
|
||||
6665b164
|
||||
ccccccce
|
||||
9999999b
|
||||
6666666d
|
||||
11111112
|
||||
bbbbbbbd
|
||||
6666666b
|
||||
66671b6a
|
||||
66666667
|
||||
cccccccc
|
||||
99999999
|
||||
bbbbbbbb
|
||||
66666669
|
||||
66671b6b
|
||||
6665b163
|
||||
cccccccd
|
||||
9999999a
|
||||
6666666c
|
||||
11111111
|
||||
bbbbbbbc
|
||||
6666666a
|
||||
3333e839
|
||||
33327e31
|
||||
9999999b
|
||||
66666668
|
||||
3333333a
|
||||
dddddddf
|
||||
8888888a
|
||||
33333338
|
||||
3333e837
|
||||
33333334
|
||||
99999999
|
||||
66666666
|
||||
88888888
|
||||
33333336
|
||||
3333e838
|
||||
33327e30
|
||||
9999999a
|
||||
66666667
|
||||
33333339
|
||||
ddddddde
|
||||
88888889
|
||||
33333337
|
||||
0000b50b
|
||||
ffff4b03
|
||||
6666666d
|
||||
3333333a
|
||||
0000000c
|
||||
aaaaaab1
|
||||
5555555c
|
||||
0000000a
|
||||
0000b509
|
||||
00000006
|
||||
6666666b
|
||||
33333338
|
||||
5555555a
|
||||
00000008
|
||||
0000b50a
|
||||
ffff4b02
|
||||
6666666c
|
||||
33333339
|
||||
0000000b
|
||||
aaaaaab0
|
||||
5555555b
|
||||
00000009
|
||||
aaab5fb0
|
||||
aaa9f5a8
|
||||
11111112
|
||||
dddddddf
|
||||
aaaaaab1
|
||||
55555556
|
||||
00000001
|
||||
aaaaaaaf
|
||||
aaab5fae
|
||||
aaaaaaab
|
||||
11111110
|
||||
dddddddd
|
||||
ffffffff
|
||||
aaaaaaad
|
||||
aaab5faf
|
||||
aaa9f5a7
|
||||
11111111
|
||||
ddddddde
|
||||
aaaaaab0
|
||||
55555555
|
||||
00000000
|
||||
aaaaaaae
|
||||
55560a5b
|
||||
5554a053
|
||||
bbbbbbbd
|
||||
8888888a
|
||||
5555555c
|
||||
00000001
|
||||
aaaaaaac
|
||||
5555555a
|
||||
55560a59
|
||||
55555556
|
||||
bbbbbbbb
|
||||
88888888
|
||||
aaaaaaaa
|
||||
55555558
|
||||
55560a5a
|
||||
5554a052
|
||||
bbbbbbbc
|
||||
88888889
|
||||
5555555b
|
||||
00000000
|
||||
aaaaaaab
|
||||
55555559
|
||||
0000b509
|
||||
ffff4b01
|
||||
6666666b
|
||||
33333338
|
||||
0000000a
|
||||
aaaaaaaf
|
||||
5555555a
|
||||
00000008
|
||||
0000b507
|
||||
00000004
|
||||
66666669
|
||||
33333336
|
||||
55555558
|
||||
00000006
|
||||
0000b508
|
||||
ffff4b00
|
||||
6666666a
|
||||
33333337
|
||||
00000009
|
||||
aaaaaaae
|
||||
55555559
|
||||
00000007
|
||||
00016a08
|
||||
00000000
|
||||
66671b6a
|
||||
3333e837
|
||||
0000b509
|
||||
aaab5fae
|
||||
55560a59
|
||||
0000b507
|
||||
00016a06
|
||||
0000b503
|
||||
66671b68
|
||||
3333e835
|
||||
55560a57
|
||||
0000b505
|
||||
00016a07
|
||||
ffffffff
|
||||
66671b69
|
||||
3333e836
|
||||
0000b508
|
||||
aaab5fad
|
||||
55560a58
|
||||
0000b506
|
||||
0000b505
|
||||
ffff4afd
|
||||
66666667
|
||||
33333334
|
||||
00000006
|
||||
aaaaaaab
|
||||
55555556
|
||||
00000004
|
||||
0000b503
|
||||
00000000
|
||||
66666665
|
||||
33333332
|
||||
55555554
|
||||
00000002
|
||||
0000b504
|
||||
ffff4afc
|
||||
66666666
|
||||
33333333
|
||||
00000005
|
||||
aaaaaaaa
|
||||
55555555
|
||||
00000003
|
||||
66671b6a
|
||||
6665b162
|
||||
cccccccc
|
||||
99999999
|
||||
6666666b
|
||||
11111110
|
||||
bbbbbbbb
|
||||
66666669
|
||||
66671b68
|
||||
66666665
|
||||
33333333
|
||||
99999998
|
||||
66666665
|
||||
88888887
|
||||
33333335
|
||||
3333e837
|
||||
33327e2f
|
||||
99999999
|
||||
66666666
|
||||
33333338
|
||||
dddddddd
|
||||
88888888
|
||||
33333336
|
||||
0000b50a
|
||||
ffff4b02
|
||||
6666666c
|
||||
33333339
|
||||
0000000b
|
||||
aaaaaab0
|
||||
5555555b
|
||||
00000009
|
||||
0000b508
|
||||
00000005
|
||||
6666666a
|
||||
33333337
|
||||
55555559
|
||||
00000007
|
||||
0000b509
|
||||
ffff4b01
|
||||
6666666b
|
||||
33333338
|
||||
0000000a
|
||||
aaaaaaaf
|
||||
5555555a
|
||||
00000008
|
||||
aaab5faf
|
||||
aaa9f5a7
|
||||
11111111
|
||||
ddddddde
|
||||
aaaaaab0
|
||||
55555555
|
||||
00000000
|
||||
aaaaaaae
|
||||
aaab5fad
|
||||
aaaaaaaa
|
||||
1111110f
|
||||
dddddddc
|
||||
fffffffe
|
||||
aaaaaaac
|
||||
aaab5fae
|
||||
aaa9f5a6
|
||||
11111110
|
||||
dddddddd
|
||||
aaaaaaaf
|
||||
55555554
|
||||
ffffffff
|
||||
aaaaaaad
|
||||
55560a5a
|
||||
5554a052
|
||||
bbbbbbbc
|
||||
88888889
|
||||
5555555b
|
||||
00000000
|
||||
aaaaaaab
|
||||
55555559
|
||||
55560a58
|
||||
55555555
|
||||
bbbbbbba
|
||||
88888887
|
||||
aaaaaaa9
|
||||
55555557
|
||||
55560a59
|
||||
5554a051
|
||||
bbbbbbbb
|
||||
88888888
|
||||
5555555a
|
||||
ffffffff
|
||||
aaaaaaaa
|
||||
55555558
|
||||
0000b508
|
||||
ffff4b00
|
||||
6666666a
|
||||
33333337
|
||||
00000009
|
||||
aaaaaaae
|
||||
55555559
|
||||
00000007
|
||||
0000b506
|
||||
00000003
|
||||
66666668
|
||||
33333335
|
||||
55555557
|
||||
00000005
|
||||
0000b507
|
||||
ffff4aff
|
||||
66666669
|
||||
33333336
|
||||
00000008
|
||||
aaaaaaad
|
||||
55555558
|
||||
00000006
|
||||
ccccccca
|
||||
99999997
|
||||
bbbbbbb9
|
||||
66666667
|
||||
66671b69
|
||||
6665b161
|
||||
cccccccb
|
||||
99999998
|
||||
6666666a
|
||||
1111110f
|
||||
bbbbbbba
|
||||
66666668
|
||||
3333e837
|
||||
33327e2f
|
||||
99999999
|
||||
66666666
|
||||
33333338
|
||||
dddddddd
|
||||
88888888
|
||||
33333336
|
||||
3333e835
|
||||
33333332
|
||||
99999997
|
||||
66666664
|
||||
88888886
|
||||
33333334
|
||||
3333e836
|
||||
33327e2e
|
||||
99999998
|
||||
66666665
|
||||
33333337
|
||||
dddddddc
|
||||
88888887
|
||||
33333335
|
||||
55560a59
|
||||
5554a051
|
||||
bbbbbbbb
|
||||
88888888
|
||||
5555555a
|
||||
ffffffff
|
||||
aaaaaaaa
|
||||
55555558
|
||||
55560a57
|
||||
55555554
|
||||
bbbbbbb9
|
||||
88888886
|
||||
aaaaaaa8
|
||||
55555556
|
||||
55560a58
|
||||
5554a050
|
||||
bbbbbbba
|
||||
88888887
|
||||
55555559
|
||||
fffffffe
|
||||
aaaaaaa9
|
||||
55555557
|
||||
0000b507
|
||||
ffff4aff
|
||||
66666669
|
||||
33333336
|
||||
00000008
|
||||
aaaaaaad
|
||||
55555558
|
||||
00000006
|
||||
0000b505
|
||||
00000002
|
||||
66666667
|
||||
33333334
|
||||
55555556
|
||||
00000004
|
||||
0000b506
|
||||
ffff4afe
|
||||
66666668
|
||||
33333335
|
||||
00000007
|
||||
aaaaaaac
|
||||
55555557
|
||||
00000005
|
||||
00016a09
|
||||
00000001
|
||||
66671b6b
|
||||
3333e838
|
||||
0000b50a
|
||||
aaab5faf
|
||||
55560a5a
|
||||
0000b508
|
||||
00016a07
|
||||
0000b504
|
||||
66671b69
|
||||
3333e836
|
||||
55560a58
|
||||
0000b506
|
||||
00016a08
|
||||
00000000
|
||||
66671b6a
|
||||
3333e837
|
||||
0000b509
|
||||
aaab5fae
|
||||
55560a59
|
||||
0000b507
|
||||
00000001
|
||||
fffe95f9
|
||||
6665b163
|
||||
33327e30
|
||||
ffff4b02
|
||||
aaa9f5a7
|
||||
5554a052
|
||||
ffff4b00
|
||||
ffffffff
|
||||
ffff4afc
|
||||
6665b161
|
||||
33327e2e
|
||||
5554a050
|
||||
ffff4afe
|
||||
00000000
|
||||
fffe95f8
|
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@ -1,375 +0,0 @@
|
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|
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@ -1,72 +0,0 @@
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@ -1,19 +0,0 @@
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@ -1,586 +0,0 @@
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|
||||
aaaaaaa8
|
||||
aaaaaaaa
|
||||
00000002
|
||||
00000000
|
||||
0000000a
|
||||
00000000
|
||||
00000002
|
||||
00000008
|
||||
aaaaaaaa
|
||||
aaaaaaaa
|
||||
00000002
|
||||
0000000a
|
||||
00000004
|
||||
55555554
|
||||
55555555
|
||||
00000005
|
||||
00000001
|
||||
00000000
|
||||
00000005
|
||||
00000000
|
||||
00000001
|
||||
55555551
|
||||
55555554
|
||||
00000001
|
||||
00000000
|
||||
00000002
|
||||
00000000
|
||||
00000003
|
||||
00000003
|
||||
00000000
|
||||
00000003
|
||||
00000000
|
||||
00000001
|
||||
00000002
|
||||
00000001
|
||||
00000003
|
||||
00000002
|
||||
00000003
|
||||
@ -1,84 +0,0 @@
|
||||
ff76df58
|
||||
ff76df5a
|
||||
ff76df5c
|
||||
ff76df5e
|
||||
ff76df60
|
||||
ff76df62
|
||||
ff76df64
|
||||
ff76df66
|
||||
ff76df68
|
||||
ff76df6a
|
||||
ff76df6c
|
||||
ff76df6e
|
||||
ff76df70
|
||||
ff76df72
|
||||
ff76df74
|
||||
ff76df76
|
||||
ff76df78
|
||||
ff76df7a
|
||||
ff76df7c
|
||||
ff76df7e
|
||||
ff76df80
|
||||
ff76df82
|
||||
ff76df84
|
||||
ff76df86
|
||||
ff76df88
|
||||
ff76df8a
|
||||
ff76df8c
|
||||
ff76df8e
|
||||
ff76df90
|
||||
ff76df92
|
||||
ff76df94
|
||||
ff76df96
|
||||
ff76df98
|
||||
ff76df9a
|
||||
ff76df9c
|
||||
ff76df9e
|
||||
ff76dfa0
|
||||
ff76dfa2
|
||||
ff76dfa4
|
||||
ff76dfa6
|
||||
ff76dfa8
|
||||
ff76dfaa
|
||||
ff76dfac
|
||||
ff76dfae
|
||||
ff76dfb0
|
||||
ff76dfb2
|
||||
ff76dfb4
|
||||
ff76dfb6
|
||||
ff76dfb8
|
||||
ff76dfba
|
||||
ff76dfbc
|
||||
ff76dfbe
|
||||
ff76dfc0
|
||||
ff76dfc2
|
||||
ff76dfc4
|
||||
ff76dfc6
|
||||
ff76dfc8
|
||||
ff76dfca
|
||||
ff76dfcc
|
||||
ff76dfce
|
||||
ff76dfd0
|
||||
ff76dfd2
|
||||
ff76dfd4
|
||||
ff76dfd6
|
||||
ff76dfd8
|
||||
ff76dfda
|
||||
ff76dfdc
|
||||
ff76dfde
|
||||
ff76dfe0
|
||||
ff76dfe2
|
||||
ff76dfe5
|
||||
ff76dfe7
|
||||
ff76dfe9
|
||||
ff76dfeb
|
||||
ff76dfed
|
||||
ff76dfef
|
||||
ff76dff1
|
||||
ff76dff3
|
||||
ff76dff5
|
||||
ff76dff7
|
||||
ff76dff9
|
||||
ff76dffb
|
||||
ff76dffd
|
||||
ff76dfff
|
||||
@ -1,84 +0,0 @@
|
||||
ff76df57
|
||||
ff76df5a
|
||||
ff76df5d
|
||||
ff76df5e
|
||||
ff76df61
|
||||
ff76df62
|
||||
ff76df63
|
||||
ff76df66
|
||||
ff76df69
|
||||
ff76df6c
|
||||
ff76df6d
|
||||
ff76df70
|
||||
ff76df73
|
||||
ff76df76
|
||||
ff76df79
|
||||
ff76df7c
|
||||
ff76df7d
|
||||
ff76df80
|
||||
ff76df81
|
||||
ff76df82
|
||||
ff76df85
|
||||
ff76df88
|
||||
ff76df89
|
||||
ff76df8a
|
||||
ff76df8d
|
||||
ff76df90
|
||||
ff76df93
|
||||
ff76df96
|
||||
ff76df97
|
||||
ff76df98
|
||||
ff76df9b
|
||||
ff76df9c
|
||||
ff76df9d
|
||||
ff76dfa0
|
||||
ff76dfa1
|
||||
ff76dfa4
|
||||
ff76dfa5
|
||||
ff76dfa8
|
||||
ff76dfa9
|
||||
ff76dfac
|
||||
ff76dfaf
|
||||
ff76dfb2
|
||||
ff76dfb3
|
||||
ff76dfb4
|
||||
ff76dfb5
|
||||
ff76dfb6
|
||||
ff76dfb7
|
||||
ff76dfba
|
||||
ff76dfbd
|
||||
ff76dfbe
|
||||
ff76dfc1
|
||||
ff76dfc2
|
||||
ff76dfc5
|
||||
ff76dfc6
|
||||
ff76dfc9
|
||||
ff76dfcc
|
||||
ff76dfcd
|
||||
ff76dfce
|
||||
ff76dfcf
|
||||
ff76dfd2
|
||||
ff76dfd5
|
||||
ff76dfd6
|
||||
ff76dfd7
|
||||
ff76dfda
|
||||
ff76dfdb
|
||||
ff76dfdc
|
||||
ff76dfdf
|
||||
ff76dfe2
|
||||
ff76dfe3
|
||||
ff76dfe6
|
||||
ff76dfe8
|
||||
ff76dfeb
|
||||
ff76dfec
|
||||
ff76dfef
|
||||
ff76dff0
|
||||
ff76dff3
|
||||
ff76dff4
|
||||
ff76dff7
|
||||
ff76dff8
|
||||
ff76dff9
|
||||
ff76dffa
|
||||
ff76dffb
|
||||
ff76dffe
|
||||
ff76e001
|
||||
@ -1,17 +0,0 @@
|
||||
ff76df57
|
||||
ff76df58
|
||||
ff76df59
|
||||
ff76df5a
|
||||
ff76df5b
|
||||
ff76df5c
|
||||
ff76df5d
|
||||
ff76df5e
|
||||
ff76df61
|
||||
ff76df64
|
||||
ff76df67
|
||||
ff76df68
|
||||
ff76df6b
|
||||
ff76df6e
|
||||
ff76df71
|
||||
ff76df74
|
||||
ff76df77
|
||||
@ -1,18 +0,0 @@
|
||||
00000015
|
||||
00000409
|
||||
00000209
|
||||
00000109
|
||||
00000089
|
||||
00000049
|
||||
00000029
|
||||
00000019
|
||||
00000011
|
||||
0000000d
|
||||
0000000d
|
||||
0000000d
|
||||
0000055d
|
||||
0000000d
|
||||
0000000d
|
||||
0000000d
|
||||
0000000d
|
||||
0000000d
|
||||
@ -1,15 +0,0 @@
|
||||
00000009
|
||||
0000000f
|
||||
00000009
|
||||
0000000f
|
||||
00000009
|
||||
0000000f
|
||||
00000009
|
||||
0000000f
|
||||
00000009
|
||||
0000000f
|
||||
00000009
|
||||
0000000f
|
||||
0000000f
|
||||
00000009
|
||||
0000000f
|
||||
@ -1,15 +0,0 @@
|
||||
00000013
|
||||
00000013
|
||||
00000013
|
||||
00000013
|
||||
00000013
|
||||
00000013
|
||||
00000013
|
||||
00000013
|
||||
00000013
|
||||
00000013
|
||||
00000013
|
||||
00000013
|
||||
00000011
|
||||
00000013
|
||||
00000011
|
||||
@ -1,17 +0,0 @@
|
||||
ffffffe0
|
||||
0000001f
|
||||
ffffffef
|
||||
fffffff7
|
||||
fffffffb
|
||||
fffffffd
|
||||
fffffffe
|
||||
00000010
|
||||
00000000
|
||||
00000008
|
||||
00000004
|
||||
00000000
|
||||
00000001
|
||||
ffffffea
|
||||
00000015
|
||||
00000000
|
||||
00000002
|
||||
@ -1,15 +0,0 @@
|
||||
00004000
|
||||
0001f000
|
||||
fffef000
|
||||
ffff7000
|
||||
ffffb000
|
||||
ffffd000
|
||||
00000000
|
||||
fffe0000
|
||||
0000c000
|
||||
00010000
|
||||
00008000
|
||||
00002000
|
||||
00001000
|
||||
fffea000
|
||||
00015000
|
||||
@ -1,13 +0,0 @@
|
||||
babecafe
|
||||
babecafe
|
||||
babecafe
|
||||
babecafe
|
||||
babecafe
|
||||
babecafe
|
||||
babecafe
|
||||
babecafe
|
||||
babecafe
|
||||
babecafe
|
||||
babecafe
|
||||
babecafe
|
||||
babecafe
|
||||
@ -1,15 +0,0 @@
|
||||
babecafe
|
||||
babecafe
|
||||
babecafe
|
||||
babecafe
|
||||
babecafe
|
||||
babecafe
|
||||
babecafe
|
||||
babecafe
|
||||
babecafe
|
||||
babecafe
|
||||
babecafe
|
||||
babecafe
|
||||
babecafe
|
||||
babecafe
|
||||
babecafe
|
||||
@ -1,85 +0,0 @@
|
||||
80000000
|
||||
7fffffff
|
||||
bfffffff
|
||||
dfffffff
|
||||
efffffff
|
||||
f7ffffff
|
||||
fbffffff
|
||||
fdffffff
|
||||
feffffff
|
||||
ff7fffff
|
||||
ffbfffff
|
||||
ffdfffff
|
||||
ffefffff
|
||||
fff7ffff
|
||||
00000000
|
||||
fffdffff
|
||||
fffeffff
|
||||
ffff7fff
|
||||
ffffbfff
|
||||
ffffdfff
|
||||
ffffefff
|
||||
fffff7ff
|
||||
fffffbff
|
||||
fffffdff
|
||||
fffffeff
|
||||
ffffff7f
|
||||
ffffffbf
|
||||
ffffffdf
|
||||
ffffffef
|
||||
fffffff7
|
||||
fffffffb
|
||||
fffffffd
|
||||
fffffffe
|
||||
40000000
|
||||
20000000
|
||||
10000000
|
||||
08000000
|
||||
04000000
|
||||
02000000
|
||||
01000000
|
||||
00800000
|
||||
00400000
|
||||
00200000
|
||||
00100000
|
||||
00080000
|
||||
00040000
|
||||
00020000
|
||||
00010000
|
||||
00008000
|
||||
00004000
|
||||
00002000
|
||||
00001000
|
||||
00000800
|
||||
00000400
|
||||
00000200
|
||||
00000100
|
||||
00000080
|
||||
00000040
|
||||
00000001
|
||||
0000b505
|
||||
ffff4afd
|
||||
66666667
|
||||
33333334
|
||||
00000006
|
||||
aaaaaaab
|
||||
55555556
|
||||
00000004
|
||||
0000b503
|
||||
00000000
|
||||
66666665
|
||||
33333332
|
||||
55555554
|
||||
00000002
|
||||
0000b504
|
||||
ffff4afc
|
||||
66666666
|
||||
33333333
|
||||
00000005
|
||||
aaaaaaaa
|
||||
55555555
|
||||
00000020
|
||||
00000010
|
||||
00000008
|
||||
00000003
|
||||
fffbffff
|
||||
@ -1,14 +0,0 @@
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
00000000
|
||||
@ -1,582 +0,0 @@
|
||||
80000000
|
||||
33333334
|
||||
bfffffff
|
||||
dfffffff
|
||||
ffffffff
|
||||
f7ffffff
|
||||
ffffffff
|
||||
fdffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffbfffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
fff7ffff
|
||||
fffbffff
|
||||
fffdffff
|
||||
ffffffff
|
||||
ffff7fff
|
||||
ffffbfff
|
||||
ffffdfff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
fffffeff
|
||||
ffffff7f
|
||||
ffffffbf
|
||||
ffffffff
|
||||
ffffffff
|
||||
fffffff7
|
||||
fffffffb
|
||||
fffffffd
|
||||
fffffffe
|
||||
7fffffff
|
||||
dfffffff
|
||||
ffffffff
|
||||
f7ffffff
|
||||
fbffffff
|
||||
fdffffff
|
||||
feffffff
|
||||
ffffffff
|
||||
ffefffff
|
||||
fffdffff
|
||||
fffeffff
|
||||
ffff7fff
|
||||
ffffbfff
|
||||
ffffdfff
|
||||
ffffefff
|
||||
fffff7ff
|
||||
ffffffff
|
||||
fffffdff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffbf
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
ffffffff
|
||||
8000b503
|
||||
40000003
|
||||
20000000
|
||||
55555554
|
||||
feffffff
|
||||
fffff7ff
|
||||
c1000000
|
||||
10800000
|
||||
fdffffff
|
||||
55755554
|
||||
bfffffff
|
||||
fffffff9
|
||||
00042000
|
||||
33333332
|
||||
00012000
|
||||
0000c000
|
||||
00002200
|
||||
04001000
|
||||
fffffffb
|
||||
00000200
|
||||
fbffffff
|
||||
04000010
|
||||
ffffffbf
|
||||
40000000
|
||||
ffff4afc
|
||||
02000010
|
||||
01000004
|
||||
ffffffff
|
||||
ffffdfff
|
||||
00300000
|
||||
00080003
|
||||
00040006
|
||||
fffeffff
|
||||
aaabaaab
|
||||
00001001
|
||||
00100800
|
||||
00020400
|
||||
ffffbfff
|
||||
00000085
|
||||
0000b505
|
||||
0000b505
|
||||
fffffffd
|
||||
6666f767
|
||||
3333b735
|
||||
0000b507
|
||||
aaaabfaf
|
||||
5555f557
|
||||
0000b505
|
||||
0000b507
|
||||
0000b505
|
||||
6666f765
|
||||
3333b737
|
||||
5555f555
|
||||
0000b507
|
||||
0000b505
|
||||
fffffffd
|
||||
6666f767
|
||||
3333b737
|
||||
0000b505
|
||||
aaaabfaf
|
||||
5555f555
|
||||
0000b507
|
||||
fffffffd
|
||||
ffff4afd
|
||||
ffff6eff
|
||||
ffff7bfd
|
||||
ffff4aff
|
||||
ffffeaff
|
||||
ffff5fff
|
||||
ffff4afd
|
||||
ffffffff
|
||||
ffff4afd
|
||||
ffff6efd
|
||||
ffff7bff
|
||||
ffff5ffd
|
||||
ffff4aff
|
||||
fffffffd
|
||||
ffff4afd
|
||||
ffff6eff
|
||||
ffff7bff
|
||||
ffff4afd
|
||||
ffffeaff
|
||||
ffff5ffd
|
||||
ffff4aff
|
||||
6666f767
|
||||
ffff6eff
|
||||
66666667
|
||||
77777777
|
||||
66666667
|
||||
eeeeeeef
|
||||
77777777
|
||||
66666667
|
||||
6666f767
|
||||
66666667
|
||||
66666667
|
||||
77777777
|
||||
77777777
|
||||
66666667
|
||||
6666f767
|
||||
ffff6eff
|
||||
66666667
|
||||
77777777
|
||||
66666667
|
||||
eeeeeeef
|
||||
77777777
|
||||
66666667
|
||||
3333b735
|
||||
ffff7bfd
|
||||
77777777
|
||||
33333334
|
||||
33333336
|
||||
bbbbbbbf
|
||||
77777776
|
||||
33333334
|
||||
3333b737
|
||||
33333334
|
||||
77777775
|
||||
33333336
|
||||
77777774
|
||||
33333336
|
||||
3333b734
|
||||
ffff7bfc
|
||||
77777776
|
||||
33333337
|
||||
33333335
|
||||
bbbbbbbe
|
||||
77777775
|
||||
33333337
|
||||
0000b507
|
||||
ffff4aff
|
||||
66666667
|
||||
33333336
|
||||
00000006
|
||||
aaaaaaaf
|
||||
55555556
|
||||
00000006
|
||||
0000b507
|
||||
00000006
|
||||
66666667
|
||||
33333336
|
||||
55555556
|
||||
00000006
|
||||
0000b506
|
||||
ffff4afe
|
||||
66666666
|
||||
33333337
|
||||
00000007
|
||||
aaaaaaae
|
||||
55555557
|
||||
00000007
|
||||
aaaabfaf
|
||||
ffffeaff
|
||||
eeeeeeef
|
||||
bbbbbbbf
|
||||
aaaaaaaf
|
||||
aaaaaaab
|
||||
ffffffff
|
||||
aaaaaaaf
|
||||
aaaabfab
|
||||
aaaaaaab
|
||||
eeeeeeef
|
||||
bbbbbbbb
|
||||
ffffffff
|
||||
aaaaaaab
|
||||
aaaabfaf
|
||||
ffffeaff
|
||||
eeeeeeef
|
||||
bbbbbbbb
|
||||
aaaaaaaf
|
||||
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|
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@ -1,86 +0,0 @@
|
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e0000000
|
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|
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|
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|
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@ -1,85 +0,0 @@
|
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@ -1,87 +0,0 @@
|
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|
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|
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|
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|
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@ -1,581 +0,0 @@
|
||||
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|
||||
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|
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|
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|
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|
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|
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|
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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|
||||
04000011
|
||||
f8800000
|
||||
00200000
|
||||
000ffffc
|
||||
f0080000
|
||||
00040001
|
||||
00020201
|
||||
e0010000
|
||||
00008008
|
||||
10002001
|
||||
10001001
|
||||
000007fb
|
||||
00000088
|
||||
ffff4b0d
|
||||
00000003
|
||||
00000000
|
||||
9999999b
|
||||
00000000
|
||||
00016a08
|
||||
999a4e9e
|
||||
cccd81d1
|
||||
0000b4ff
|
||||
55560a5a
|
||||
aaab5faf
|
||||
0000b501
|
||||
00000002
|
||||
0000b505
|
||||
999a4ea0
|
||||
cccd81d3
|
||||
aaab5fb1
|
||||
0000b503
|
||||
00000001
|
||||
00016a09
|
||||
999a4e9f
|
||||
cccd81d2
|
||||
0000b500
|
||||
55560a5b
|
||||
aaab5fb0
|
||||
0000b502
|
||||
fffe95f8
|
||||
00000000
|
||||
9998e496
|
||||
cccc17c9
|
||||
ffff4af7
|
||||
5554a052
|
||||
aaa9f5a7
|
||||
ffff4af9
|
||||
fffe95fa
|
||||
ffff4afd
|
||||
9998e498
|
||||
cccc17cb
|
||||
aaa9f5a9
|
||||
ffff4afb
|
||||
fffe95f9
|
||||
00000001
|
||||
9998e497
|
||||
cccc17ca
|
||||
ffff4af8
|
||||
5554a053
|
||||
aaa9f5a8
|
||||
ffff4afa
|
||||
6665b162
|
||||
66671b6a
|
||||
00000000
|
||||
33333333
|
||||
66666661
|
||||
bbbbbbbc
|
||||
11111111
|
||||
66666663
|
||||
6665b164
|
||||
66666667
|
||||
00000002
|
||||
33333335
|
||||
11111113
|
||||
66666665
|
||||
6665b163
|
||||
66671b6b
|
||||
00000001
|
||||
33333334
|
||||
66666662
|
||||
bbbbbbbd
|
||||
11111112
|
||||
66666664
|
||||
33327e2f
|
||||
3333e837
|
||||
cccccccd
|
||||
00000000
|
||||
3333332e
|
||||
88888889
|
||||
ddddddde
|
||||
33333330
|
||||
33327e31
|
||||
33333334
|
||||
cccccccf
|
||||
00000002
|
||||
dddddde0
|
||||
33333332
|
||||
33327e30
|
||||
3333e838
|
||||
ccccccce
|
||||
00000001
|
||||
3333332f
|
||||
8888888a
|
||||
dddddddf
|
||||
33333331
|
||||
ffff4b01
|
||||
0000b509
|
||||
9999999f
|
||||
ccccccd2
|
||||
00000000
|
||||
5555555b
|
||||
aaaaaab0
|
||||
00000002
|
||||
ffff4b03
|
||||
00000006
|
||||
999999a1
|
||||
ccccccd4
|
||||
aaaaaab2
|
||||
00000004
|
||||
ffff4b02
|
||||
0000b50a
|
||||
999999a0
|
||||
ccccccd3
|
||||
00000001
|
||||
5555555c
|
||||
aaaaaab1
|
||||
00000003
|
||||
aaa9f5a6
|
||||
aaab5fae
|
||||
44444444
|
||||
77777777
|
||||
aaaaaaa5
|
||||
00000000
|
||||
55555555
|
||||
aaaaaaa7
|
||||
aaa9f5a8
|
||||
aaaaaaab
|
||||
44444446
|
||||
77777779
|
||||
55555557
|
||||
aaaaaaa9
|
||||
aaa9f5a7
|
||||
aaab5faf
|
||||
44444445
|
||||
77777778
|
||||
aaaaaaa6
|
||||
00000001
|
||||
55555556
|
||||
aaaaaaa8
|
||||
5554a051
|
||||
55560a59
|
||||
eeeeeeef
|
||||
22222222
|
||||
55555550
|
||||
aaaaaaab
|
||||
00000000
|
||||
55555552
|
||||
5554a053
|
||||
55555556
|
||||
eeeeeef1
|
||||
22222224
|
||||
00000002
|
||||
55555554
|
||||
5554a052
|
||||
55560a5a
|
||||
eeeeeef0
|
||||
22222223
|
||||
55555551
|
||||
aaaaaaac
|
||||
00000001
|
||||
55555553
|
||||
ffff4aff
|
||||
0000b507
|
||||
9999999d
|
||||
ccccccd0
|
||||
fffffffe
|
||||
55555559
|
||||
aaaaaaae
|
||||
00000000
|
||||
ffff4b01
|
||||
00000004
|
||||
9999999f
|
||||
ccccccd2
|
||||
aaaaaab0
|
||||
00000002
|
||||
ffff4b00
|
||||
0000b508
|
||||
9999999e
|
||||
ccccccd1
|
||||
ffffffff
|
||||
5555555a
|
||||
aaaaaaaf
|
||||
00000001
|
||||
fffffffe
|
||||
00016a06
|
||||
999a4e9c
|
||||
cccd81cf
|
||||
0000b4fd
|
||||
55560a58
|
||||
aaab5fad
|
||||
0000b4ff
|
||||
00000000
|
||||
0000b503
|
||||
999a4e9e
|
||||
cccd81d1
|
||||
aaab5faf
|
||||
0000b501
|
||||
ffffffff
|
||||
00016a07
|
||||
999a4e9d
|
||||
cccd81d0
|
||||
0000b4fe
|
||||
55560a59
|
||||
aaab5fae
|
||||
0000b500
|
||||
ffff4afb
|
||||
0000b503
|
||||
99999999
|
||||
cccccccc
|
||||
fffffffa
|
||||
55555555
|
||||
aaaaaaaa
|
||||
fffffffc
|
||||
ffff4afd
|
||||
00000000
|
||||
9999999b
|
||||
ccccccce
|
||||
aaaaaaac
|
||||
fffffffe
|
||||
ffff4afc
|
||||
0000b504
|
||||
9999999a
|
||||
cccccccd
|
||||
fffffffb
|
||||
55555556
|
||||
aaaaaaab
|
||||
fffffffd
|
||||
6665b160
|
||||
66671b68
|
||||
fffffffe
|
||||
33333331
|
||||
6666665f
|
||||
bbbbbbba
|
||||
1111110f
|
||||
33333333
|
||||
ccccccce
|
||||
00000001
|
||||
dddddddf
|
||||
33333331
|
||||
33327e2f
|
||||
3333e837
|
||||
cccccccd
|
||||
00000000
|
||||
3333332e
|
||||
88888889
|
||||
ddddddde
|
||||
33333330
|
||||
ffff4b00
|
||||
0000b508
|
||||
9999999e
|
||||
ccccccd1
|
||||
ffffffff
|
||||
5555555a
|
||||
aaaaaaaf
|
||||
00000001
|
||||
ffff4b02
|
||||
00000005
|
||||
999999a0
|
||||
ccccccd3
|
||||
aaaaaab1
|
||||
00000003
|
||||
ffff4b01
|
||||
0000b509
|
||||
9999999f
|
||||
ccccccd2
|
||||
00000000
|
||||
5555555b
|
||||
aaaaaab0
|
||||
00000002
|
||||
aaa9f5a5
|
||||
aaab5fad
|
||||
44444443
|
||||
77777776
|
||||
aaaaaaa4
|
||||
ffffffff
|
||||
55555554
|
||||
aaaaaaa6
|
||||
aaa9f5a7
|
||||
aaaaaaaa
|
||||
44444445
|
||||
77777778
|
||||
55555556
|
||||
aaaaaaa8
|
||||
aaa9f5a6
|
||||
aaab5fae
|
||||
44444444
|
||||
77777777
|
||||
aaaaaaa5
|
||||
00000000
|
||||
55555555
|
||||
aaaaaaa7
|
||||
5554a050
|
||||
55560a58
|
||||
eeeeeeee
|
||||
22222221
|
||||
5555554f
|
||||
aaaaaaaa
|
||||
ffffffff
|
||||
55555551
|
||||
5554a052
|
||||
55555555
|
||||
eeeeeef0
|
||||
22222223
|
||||
00000001
|
||||
55555553
|
||||
5554a051
|
||||
55560a59
|
||||
eeeeeeef
|
||||
22222222
|
||||
55555550
|
||||
aaaaaaab
|
||||
00000000
|
||||
55555552
|
||||
ffff4afe
|
||||
0000b506
|
||||
9999999c
|
||||
cccccccf
|
||||
fffffffd
|
||||
55555558
|
||||
aaaaaaad
|
||||
ffffffff
|
||||
ffff4b00
|
||||
00000003
|
||||
9999999e
|
||||
ccccccd1
|
||||
aaaaaaaf
|
||||
00000001
|
||||
ffff4aff
|
||||
0000b507
|
||||
9999999d
|
||||
ccccccd0
|
||||
fffffffe
|
||||
55555559
|
||||
aaaaaaae
|
||||
00000000
|
||||
66666661
|
||||
6665b162
|
||||
66666665
|
||||
00000000
|
||||
33333333
|
||||
11111111
|
||||
66666663
|
||||
6665b161
|
||||
66671b69
|
||||
ffffffff
|
||||
33333332
|
||||
66666660
|
||||
bbbbbbbb
|
||||
11111110
|
||||
66666662
|
||||
33327e2d
|
||||
3333e835
|
||||
cccccccb
|
||||
fffffffe
|
||||
3333332c
|
||||
88888887
|
||||
dddddddc
|
||||
3333332e
|
||||
33327e2f
|
||||
33333332
|
||||
cccccccd
|
||||
00000000
|
||||
ddddddde
|
||||
33333330
|
||||
33327e2e
|
||||
3333e836
|
||||
cccccccc
|
||||
ffffffff
|
||||
3333332d
|
||||
88888888
|
||||
dddddddd
|
||||
3333332f
|
||||
5554a04f
|
||||
55560a57
|
||||
eeeeeeed
|
||||
22222220
|
||||
5555554e
|
||||
aaaaaaa9
|
||||
fffffffe
|
||||
55555550
|
||||
5554a051
|
||||
55555554
|
||||
eeeeeeef
|
||||
22222222
|
||||
00000000
|
||||
55555552
|
||||
5554a050
|
||||
55560a58
|
||||
eeeeeeee
|
||||
22222221
|
||||
5555554f
|
||||
aaaaaaaa
|
||||
ffffffff
|
||||
55555551
|
||||
ffff4afd
|
||||
0000b505
|
||||
9999999b
|
||||
ccccccce
|
||||
fffffffc
|
||||
55555557
|
||||
aaaaaaac
|
||||
fffffffe
|
||||
ffff4aff
|
||||
00000002
|
||||
9999999d
|
||||
ccccccd0
|
||||
aaaaaaae
|
||||
ffff4afe
|
||||
0000b506
|
||||
9999999c
|
||||
cccccccf
|
||||
fffffffd
|
||||
55555558
|
||||
aaaaaaad
|
||||
ffffffff
|
||||
ffffffff
|
||||
00016a07
|
||||
999a4e9d
|
||||
cccd81d0
|
||||
0000b4fe
|
||||
55560a59
|
||||
aaab5fae
|
||||
0000b500
|
||||
00000001
|
||||
0000b504
|
||||
999a4e9f
|
||||
cccd81d2
|
||||
aaab5fb0
|
||||
0000b502
|
||||
00000000
|
||||
00016a08
|
||||
999a4e9e
|
||||
cccd81d1
|
||||
0000b4ff
|
||||
55560a5a
|
||||
aaab5faf
|
||||
0000b501
|
||||
fffe95f7
|
||||
ffffffff
|
||||
9998e495
|
||||
cccc17c8
|
||||
ffff4af6
|
||||
5554a051
|
||||
aaa9f5a6
|
||||
fffe95f9
|
||||
ffff4afc
|
||||
9998e497
|
||||
cccc17ca
|
||||
aaa9f5a8
|
||||
ffff4afa
|
||||
fffe95f8
|
||||
00000000
|
||||
9998e496
|
||||
cccc17c9
|
||||
ffff4af7
|
||||
5554a052
|
||||
aaa9f5a7
|
||||
ffff4af9
|
||||
6665b161
|
||||
66671b69
|
||||
ffffffff
|
||||
33333332
|
||||
66666660
|
||||
bbbbbbbb
|
||||
11111110
|
||||
66666662
|
||||
6665b163
|
||||
66666666
|
||||
00000001
|
||||
33333334
|
||||
11111112
|
||||
66666664
|
||||
6665b162
|
||||
66671b6a
|
||||
00000000
|
||||
33333333
|
||||
66666661
|
||||
bbbbbbbc
|
||||
11111111
|
||||
66666663
|
||||
33327e2e
|
||||
3333e836
|
||||
cccccccc
|
||||
ffffffff
|
||||
3333332d
|
||||
88888888
|
||||
dddddddd
|
||||
3333332f
|
||||
33327e30
|
||||
7fffff00
|
||||
@ -1,68 +0,0 @@
|
||||
ffffbfff
|
||||
7fffffff
|
||||
bfffffff
|
||||
dfffffff
|
||||
efffffff
|
||||
f7ffffff
|
||||
fbffffff
|
||||
fdffffff
|
||||
feffffff
|
||||
ff7fffff
|
||||
ffbfffff
|
||||
ffdfffff
|
||||
ffefffff
|
||||
fff7ffff
|
||||
fffbffff
|
||||
fffdffff
|
||||
fffeffff
|
||||
ffff7fff
|
||||
ffffdfff
|
||||
ffffefff
|
||||
fffff7ff
|
||||
fffffbff
|
||||
fffffdff
|
||||
fffffeff
|
||||
ffffff7f
|
||||
ffffffbf
|
||||
ffffffdf
|
||||
ffffffef
|
||||
fffffff7
|
||||
fffffffb
|
||||
fffffffd
|
||||
fffffffe
|
||||
00008000
|
||||
80000000
|
||||
40000000
|
||||
20000000
|
||||
10000000
|
||||
08000000
|
||||
00000020
|
||||
00000010
|
||||
00000008
|
||||
00000004
|
||||
00000002
|
||||
00000001
|
||||
ffefffff
|
||||
00080000
|
||||
aaaaaaaa
|
||||
55555555
|
||||
00000000
|
||||
04000000
|
||||
02000000
|
||||
01000000
|
||||
00800000
|
||||
00400000
|
||||
00200000
|
||||
00100000
|
||||
00040000
|
||||
00020000
|
||||
00010000
|
||||
00004000
|
||||
00002000
|
||||
00001000
|
||||
00000800
|
||||
00000400
|
||||
00000200
|
||||
00000100
|
||||
00000080
|
||||
00000040
|
||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue
Block a user