bbracker
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ced5039776
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Revert "fixed forwarding"
This reverts commit 0f4a4a6ade .
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2021-06-24 17:39:37 -04:00 |
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bbracker
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0f4a4a6ade
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fixed forwarding
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2021-06-24 11:20:21 -04:00 |
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Ross Thompson
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d5063bee7d
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Updated icache to abhlite to use pa_bits length and moved F/D stage instr register to ifu from icache.
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2021-06-23 15:13:56 -05:00 |
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David Harris
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1972d83002
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Refactored pmachecker to have adrdecs used in uncore
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2021-06-23 01:41:00 -04:00 |
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David Harris
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6dc54acde8
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renamed dmem to lsu and removed adrdec module from pmpadrdec
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2021-06-22 23:03:43 -04:00 |
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bbracker
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ae0fa90450
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-06-22 18:28:30 -04:00 |
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bbracker
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b43a8885cd
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give EBU a dedicated PMA unit as just an address decoder
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2021-06-22 18:28:08 -04:00 |
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Katherine Parry
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9eb6eb40bf
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rv64f FLW passes imperas tests
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2021-06-22 16:36:16 -04:00 |
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David Harris
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aef408af58
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Reversed [0:...] with [...:0] in bus widths across the project
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2021-06-21 01:17:08 -04:00 |
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David Harris
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21a55458ca
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Made MemPAdrM and related signals PA_BITS wide
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2021-06-18 09:36:22 -04:00 |
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David Harris
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e03912f64c
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Cleaned up name of MTIME register in CSRC
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2021-06-18 07:53:49 -04:00 |
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bbracker
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7d1469a06c
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provide time and timeh CSRs based on CLINT's counter
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2021-06-17 08:38:30 -04:00 |
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David Harris
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9a17556de4
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Start to parameterize number of PMP Entries
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2021-06-08 15:29:22 -04:00 |
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bbracker
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17960a6484
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Ah big ole merge! Passes sim-wally-batch and linting, so should be fine
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2021-06-08 12:41:25 -04:00 |
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bbracker
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5026a42fac
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* GPIO comprehensive testing
* MEPC more aware if M stage has actually committed
* UART interrupt testing progress
* UART added read IIR side effect of lowering THRE intr
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2021-06-08 12:32:46 -04:00 |
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David Harris
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1e67db2f0c
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Second attept to commit refactoring config files
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2021-06-07 12:37:46 -04:00 |
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Katherine Parry
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e4db6ea6f5
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fixed lint warnings for fpu and lzd
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2021-06-05 12:06:33 -04:00 |
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Kip Macsai-Goren
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d69501c4fa
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Cleaned up some unused signals
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2021-06-04 21:04:19 -04:00 |
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Kip Macsai-Goren
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7e41b17e65
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restructured so that pma/pmp are a part of mmu
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2021-06-04 17:05:07 -04:00 |
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bbracker
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28abd28b1f
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fixed InstrValid signals and implemented less costly MEPC loading
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2021-06-02 10:03:19 -04:00 |
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bbracker
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a45b61ede9
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turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
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2021-05-28 23:11:37 -04:00 |
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Katherine Parry
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65eca433b6
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All compare instructions pass imperas tests
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2021-05-27 15:23:28 -04:00 |
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Katherine Parry
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3869a73a9c
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renamed top level FPU wires
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2021-05-25 20:04:34 -04:00 |
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Katherine Parry
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03aea055fa
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FMV.X.D imperas test passes
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2021-05-24 14:44:30 -04:00 |
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Katherine Parry
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55f22979ca
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FSD and FLD imperas tests pass
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2021-05-23 18:33:14 -04:00 |
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Katherine Parry
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71e4a10efb
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FMV.D.X imperas test passes
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2021-05-20 22:17:59 -04:00 |
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Katherine Parry
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409438bc95
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floating point infinite loop removed from imperas tests
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2021-05-18 10:42:51 -04:00 |
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Thomas Fleming
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1fc607b399
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Remove busy-mmu and fix missing signal
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2021-05-14 07:14:20 -04:00 |
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Thomas Fleming
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94d734cca9
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
Conflicts:
wally-pipelined/src/ebu/ahblite.sv
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2021-05-03 14:02:19 -04:00 |
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Katherine Parry
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9252d08b41
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fpu imperas tests run
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2021-05-01 02:18:01 +00:00 |
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Thomas Fleming
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e091f430e0
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Clean up PMA checker and begin PMP checker
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2021-04-29 02:20:39 -04:00 |
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Ross Thompson
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9e40fb072c
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Merge branch 'tests' into icache-almost-working
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2021-04-25 21:25:36 -05:00 |
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Ross Thompson
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d7fea1ba3c
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almost working icache.
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2021-04-23 16:47:23 -05:00 |
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Ross Thompson
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c9bdaceddb
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Fixed icache for 32 bit.
Merge branch 'cache' into main
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2021-04-22 16:45:29 -05:00 |
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Thomas Fleming
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e7822ce20c
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Implement first pass at the PMA checker
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2021-04-22 15:34:02 -04:00 |
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Thomas Fleming
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4d4ca24640
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Extend stall on leaf page lookups
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2021-04-22 01:51:38 -04:00 |
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Thomas Fleming
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70c801331a
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Implement virtual memory protection
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2021-04-21 19:58:36 -04:00 |
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Jarred Allen
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757b64e487
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Merge branch 'main' into cache
Conflicts:
wally-pipelined/src/cache/dmapped.sv
wally-pipelined/src/cache/line.sv
wally-pipelined/src/ifu/icache.sv
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2021-04-14 18:24:32 -04:00 |
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Thomas Fleming
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ae888b5705
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
Conflicts:
wally-pipelined/src/ebu/pagetablewalker.sv
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2021-04-13 13:42:03 -04:00 |
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Thomas Fleming
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f0c926cf68
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Move InstrPageFault to fetch stage
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2021-04-13 13:39:22 -04:00 |
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Teo Ene
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0bffac2c74
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Various code syntax changes to bring HDL to a synthesizable level
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2021-04-13 11:27:12 -05:00 |
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Jarred Allen
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6ce4d44ae1
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Merge from branch 'main'
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2021-04-08 17:19:34 -04:00 |
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Thomas Fleming
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e807f5d771
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Implement support for superpages
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2021-04-08 02:44:59 -04:00 |
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Ross Thompson
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d901cfc848
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Merge branch 'icache_bp_bug' into tests
Not sure this merge is right.
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2021-04-06 21:46:40 -05:00 |
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Thomas Fleming
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5946b860ca
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Comment out fpu from hart until module exists
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2021-04-03 22:34:11 -04:00 |
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Thomas Fleming
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8f31e00f6a
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Merge branch 'mmu' into main
Conflicts:
wally-pipelined/src/wally/wallypipelinedhart.sv
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2021-04-03 22:12:52 -04:00 |
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Thomas Fleming
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e04ad8f304
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Fix extraneous page fault stall
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2021-04-03 21:28:24 -04:00 |
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Katherine Parry
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08b31f7b2a
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Integrated FPU
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2021-04-03 20:52:26 +00:00 |
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James E. Stine
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9026357350
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Added some updates to divider - still not working all the time. Still a bug with signals within muldiv - specificaly MultDivE being modified during Execute stage. Seems to be triggered by ahblite signal.
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2021-04-02 06:27:37 -05:00 |
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Thomas Fleming
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f9bf2fbc01
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Implement sfence.vma and fix tlb writing
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2021-04-01 15:55:05 -04:00 |
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