Kip Macsai-Goren
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a82c0a7780
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Modified virt mem tests to do correct r/w when svadu is enabled
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2023-04-11 18:08:30 -07:00 |
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Kip Macsai-Goren
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4aed880757
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enabled SVADU for rv32/64gc
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2023-04-11 17:42:26 -07:00 |
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Kip Macsai-Goren
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e0b938b409
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Removed Trap outputs from writes covered by SVADU
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2023-04-11 17:41:57 -07:00 |
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Kip Macsai-Goren
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a899606c2b
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Removed Sail from virt mem tests due to sail not recognizing SVADU
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2023-04-11 17:41:31 -07:00 |
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Kip Macsai-Goren
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19305fe60a
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Added sail simulation to priv tests that support it
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2023-04-11 13:26:59 -07:00 |
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David Harris
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83f5005738
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Merge pull request #230 from ACWright256/main
Excluded coverage for misaligned instructions
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2023-04-11 05:21:09 -07:00 |
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Alexa Wright
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fb517163f5
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Excluded coverage for misaligned instructions
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2023-04-10 23:18:25 -07:00 |
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David Harris
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90c9f29beb
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Merge pull request #226 from SydRiley/main
Increased coverage for the fpu by adding directed tests to toggle signals
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2023-04-09 21:52:11 -07:00 |
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David Harris
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adcc22de9d
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Merge pull request #223 from ross144/main
Solves issue 172
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2023-04-09 20:30:26 -07:00 |
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David Harris
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23380f343d
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Merge pull request #224 from kbox13/my-single-change
Create new PMP tests
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2023-04-09 20:29:03 -07:00 |
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Kevin Box
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59e7c9371a
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Create new pmp tests
configures all pmpcfg registers in each different address range.
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2023-04-09 16:29:57 -07:00 |
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Sydeny
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f4caa62efc
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Increasing coverage for the fpu by adding directed tests to toggle signals
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2023-04-09 13:33:12 -07:00 |
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Ross Thompson
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009a020c88
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Updated wally figure again to increase resolution.
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2023-04-09 12:26:15 -05:00 |
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Ross Thompson
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1534ae1879
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Updated wally top level figure to fix issue 172.
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2023-04-09 12:20:43 -05:00 |
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Ross Thompson
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81074a822a
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Merge branch 'main' of https://github.com/openhwgroup/cvw into main
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2023-04-09 12:19:44 -05:00 |
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David Harris
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c197739841
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Merge pull request #222 from kjprime/main
Remove unnecessary check from compressed instruction decode
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2023-04-09 04:56:21 -07:00 |
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David Harris
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df2943b9c1
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Merge pull request #221 from dherreravicioso/main
Added test coverage for Privilege Unit in CSRs
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2023-04-09 04:54:36 -07:00 |
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Kevin Thomas
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f7838b869b
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-04-08 22:56:20 -05:00 |
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Diego Herrera Vicioso
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5f9c443781
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Added test coverage for floating point registers, some PMP addresses, as well as MTVAL and MCAUSE CSRs.
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2023-04-08 16:40:36 -07:00 |
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Ross Thompson
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ba08c39eef
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Merge pull request #220 from davidharrishmc/dev
Obscure coverage fixes
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2023-04-08 10:27:31 -05:00 |
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David Harris
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1c47221983
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-04-07 21:57:18 -07:00 |
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David Harris
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7affe2bdca
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Waived coverage on BTB memory with byte write enables tied high
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2023-04-07 21:56:49 -07:00 |
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David Harris
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2f4074b9c2
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Improved RAS predictor coverage by eliminating unreachable StallM term
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2023-04-07 21:37:12 -07:00 |
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Ross Thompson
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cfab7c8b45
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Merge pull request #219 from davidharrishmc/dev
Spill logic coverage and fdivsqrt cleanup
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2023-04-07 23:30:52 -05:00 |
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David Harris
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5cdd3d57c7
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Commented WFI non-flush in writeback stage of hazard unit
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2023-04-07 21:27:13 -07:00 |
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David Harris
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b27199e276
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Added vm64check tests to cover IMMU vm64
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2023-04-07 21:14:52 -07:00 |
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David Harris
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0d2de13990
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Fixed csrwrites.S to agree with ImperasDV. Now coverage tests pass iter-elf
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2023-04-07 21:11:01 -07:00 |
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David Harris
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bf9db11a57
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Fixed priv.S to initialize stimecmp and agree with ImperasDV
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2023-04-07 20:44:01 -07:00 |
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David Harris
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9394389fec
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Bug fix: MTIME & MTIMEH registers are unimplemented and should fault when accessed
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2023-04-07 20:43:28 -07:00 |
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David Harris
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16eca598ba
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Fixed WALLY-init-lib to return correctly even from traps from compressed instructions
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2023-04-07 20:24:33 -07:00 |
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David Harris
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a49f1f785e
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Fixed enabling machine timer interrupt
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2023-04-06 22:18:33 -07:00 |
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David Harris
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8ef9891e46
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vm64 tests
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2023-04-06 21:42:47 -07:00 |
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David Harris
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19c39628fa
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Division cleanup
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2023-04-06 21:42:34 -07:00 |
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David Harris
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6db65f30b1
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Simplified integer division preprocessing in fdivsqrt
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2023-04-06 16:43:28 -07:00 |
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David Harris
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4ce223281a
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-04-06 14:07:59 -07:00 |
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David Harris
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7ad05d9a42
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Removed redundant stall signal to get spill coverage
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2023-04-06 14:07:50 -07:00 |
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Ross Thompson
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a0471dd8bd
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Merge branch 'main' of github.com:ross144/cvw
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2023-04-06 15:33:24 -05:00 |
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Ross Thompson
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6cdfbef2ca
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Added Jacob's ILA script.
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2023-04-06 15:32:36 -05:00 |
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Ross Thompson
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07b946bc75
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Fixed syntax error.
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2023-04-06 15:10:55 -05:00 |
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Ross Thompson
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4407d3310c
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Added note about strange vivado behavior not inferring block ram.
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2023-04-06 15:09:35 -05:00 |
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Ross Thompson
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ee4cf5e94d
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Similifed the no byte write enabled version of the sram model.
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2023-04-06 14:18:41 -05:00 |
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Kevin Thomas
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a588a9eb5d
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-04-06 12:38:41 -05:00 |
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David Harris
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17f96aa341
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Update dvtestplan.md
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2023-04-06 09:29:47 -07:00 |
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David Harris
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beade59349
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Create dvtestplan.md
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2023-04-06 09:23:09 -07:00 |
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David Harris
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1300d57d33
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Merge pull request #214 from eroom1966/main
Add in configuration for B extension
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2023-04-06 09:08:20 -07:00 |
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Lee Moore
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83609218aa
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Merge branch 'openhwgroup:main' into main
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2023-04-06 16:31:49 +01:00 |
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eroom1966
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dc79710724
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add support into configuration for Zb(a,b,c,s)
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2023-04-06 16:30:14 +01:00 |
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David Harris
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1d39c4f823
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Merge pull request #213 from eroom1966/main
fix break to simulation testbench
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2023-04-06 06:54:59 -07:00 |
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eroom1966
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47999784d6
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fix break to simulation testbench
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2023-04-06 14:45:41 +01:00 |
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David Harris
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4e3af7bca7
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Merge pull request #211 from ross144/main
Fixes the issue introduced by the fix for issue 203
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2023-04-05 21:50:32 -07:00 |
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