646 Commits

Author	SHA1	Message	Date
Ross Thompson	a79e5e11f6	Merged together the cache speed updates with the cache sram changes. The fstore2 changes still need to be added.	2022-07-18 23:37:18 -05:00
Ross Thompson	0ef6137ab9	Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN.	2022-07-17 21:05:31 -05:00
Ross Thompson	8356e5d742	Updated cache sram's to use 1 sram for all words in a way. Still needs to modified to support subdivision by max physical sram width.	2022-07-17 16:20:04 -05:00
David Harris	622773343f	restored intPending logic to be sticky for PLIC	2022-07-16 17:43:31 -07:00
Katherine Parry	e3ed40620c	forgot some files	2022-07-15 21:42:45 +00:00
Katherine Parry	5cb9c9f319	merged floating-point radix-2 divider with radix-4	2022-07-15 20:16:59 +00:00
Katherine Parry	2fe8b6e34c	fixed error in divsqrt	2022-07-14 18:16:00 +00:00
Katherine Parry	66bef379cb	renamed a file to fit diagram	2022-07-13 23:44:54 +00:00
Katherine Parry	3dcddf8453	some code cleanup	2022-07-13 15:28:22 -07:00
Katherine Parry	b874c5c05d	removed minus 1 case in rounding	2022-07-13 15:01:38 -07:00
Katherine Parry	b45b3baec2	removed the +1 in the cvt	2022-07-13 09:41:35 -07:00
Katherine Parry	3c1bea1104	removed warnings and took a mux out of the critical path	2022-07-12 18:32:17 -07:00
Katherine Parry	12a54161c0	found the bug in the store modification	2022-07-12 22:42:19 +00:00
Katherine Parry	18d7fee541	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-12 22:37:20 +00:00
Katherine Parry	1267d33d3c	forgot a file	2022-07-11 18:31:51 -07:00
Katherine Parry	ba339fc794	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-07-11 18:30:29 -07:00
Katherine Parry	bea4ec078d	variable interations implemented in radix-4 divider	2022-07-11 18:30:21 -07:00
David Harris	03a20610aa	added comment about checking SRAM size	2022-07-10 12:48:51 +00:00
David Harris	d1a7832dd9	added comment about RAMs in cacheway	2022-07-10 12:47:34 +00:00
Katherine Parry	62205ebb3b	renamed FLoad2 to FStore2	2022-07-09 00:26:45 +00:00
Katherine Parry	97e7e619d9	moved fpu ieu write data mux to lsu	2022-07-08 23:56:57 +00:00
Katherine Parry	c56fdd7e0f	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-07-08 12:30:50 -07:00
Katherine Parry	88b4f9b40a	renamed signals in cvt and prostproc	2022-07-08 12:30:43 -07:00
James Stine	99fed5d59f	Update SRAM to /proj/wally	2022-07-08 08:09:55 -05:00
David Harris	87ea95e6c5	erge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-08 09:09:07 +00:00
David Harris	5ae88dbef0	Moved HWSTRB to ahblite, factored out of peripherals. Moved old AHB peripherals to unusedsrc	2022-07-08 09:09:02 +00:00
David Harris	96cc66d151	Adjusting byte writes to RAM	2022-07-08 08:45:21 +00:00
David Harris	38ef8eebbb	Removed subwordwrite mention in cache because sww is needed to replicate data across byte enables	2022-07-08 08:44:37 +00:00
David Harris	234175f236	Removed unused swbytemask from CLINT	2022-07-08 08:43:24 +00:00
Katherine Parry	b67792086c	moved unsused division code again	2022-07-07 16:41:26 -07:00
Katherine Parry	b1e2a1e5a1	Revert "moved old divsqrt to unusedsrc" ... This reverts commit 5dd07c76bd.	2022-07-07 16:29:17 -07:00
Katherine Parry	5dd07c76bd	moved old divsqrt to unusedsrc	2022-07-07 16:09:56 -07:00
Katherine Parry	75a8cea4e4	srt divider merged into fpu	2022-07-07 16:01:33 -07:00
David Harris	425fec0f41	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-07 22:00:59 +00:00
Katherine Parry	c581fba4aa	modified wally shared	2022-07-07 21:59:43 +00:00
David Harris	f865994ba1	fixing port errors	2022-07-07 21:57:10 +00:00
Katherine Parry	7771f7b3eb	added load and store test	2022-07-07 21:48:51 +00:00
David Harris	f2915129ab	Preliminary SRAM integration	2022-07-07 19:56:20 +00:00
David Harris	21fb120aac	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-06 23:43:05 +00:00
Ross Thompson	d716c25275	Fixed an issue with direct map cache's nextway logic. ... Also found a small error in the replacement policy.	2022-07-06 18:34:30 -05:00
Madeleine Masser-Frye	ad29e19a27	fixed width mismatch for rv64 ieuadrM and readdatawordM	2022-07-06 22:39:35 +00:00
David Harris	529f48ed58	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally	2022-07-06 13:26:26 +00:00
David Harris	76302a8599	PLIC and UART passing tests on APB	2022-07-06 13:26:14 +00:00
Madeleine Masser-Frye	52562c9190	new priority onehot module for better area/time	2022-07-06 00:08:59 +00:00
Madeleine Masser-Frye	b5454f3a55	took first match out of pmpadrdec	2022-07-06 00:02:01 +00:00
Madeleine Masser-Frye	d8ea12c6f4	fixed concatenation syntax	2022-07-05 22:36:54 +00:00
David Harris	72e216d053	APB CLINT passing regression	2022-07-05 15:51:35 +00:00
David Harris	5f5ad77d4a	Modified uncore to use AHB bridge to GPIO	2022-07-05 05:02:21 +00:00
David Harris	c8ac05ba7b	AHB bridge for gpio	2022-07-05 05:01:59 +00:00
David Harris	ca95b46de5	Added reference to Schmookler01 for LOA	2022-07-05 05:01:12 +00:00