16 Commits

Author	SHA1	Message	Date
Rose Thompson	a7dd2eff01	Switch rv64gc_CacheSim.py to use verilator as the default sim rather than questa.	2024-11-13 12:29:02 -06:00
Rose Thompson	7868af0f81	Code cleanup.	2024-11-12 17:43:09 -06:00
Rose Thompson	8659d6efdb	Resolved all CacheSim.py vs Wally mismaches.	2024-11-12 17:24:06 -06:00
Rose Thompson	b7b7c79726	CBO.FLUSH was not clearing the valid bit if the cacheline was clean.	2024-11-12 14:16:55 -06:00
Rose Thompson	5cc1fd4a85	Getting closer. Oly the wally64priv tests mismatch between the cachesim and wally.	2024-11-12 12:08:14 -06:00
Rose Thompson	8a4868ac57	Resolved a bug in the cache but there are still mismatches with the cache simulator.	2024-11-12 11:35:29 -06:00
Jordan Carlin	78bd6822c6	Add --params argument to wsim and use for overriding top-level params	2024-08-11 13:08:16 -07:00
Jordan Carlin	e6ddebde72	Add number of mismatches exit code to cachesim scripts	2024-08-11 11:02:23 -07:00
Jordan Carlin	4ffd10bbb8	Automatically enable I_CACHE_ADDR_LOGGER and I_CACHE_ADDR_LOGGER in rv64gc_CacheSim.py. Working for Questa and Verilator.	2024-08-10 12:21:44 -07:00
Jordan Carlin	9a70480ef6	Update CacheSim scripts with new wsim and directory structure. Give simulator choice and switch default to verilator.	2024-08-09 21:50:18 -07:00
David Harris	45e2317636	Added Wally github address to header comments	2024-01-29 05:38:11 -08:00
David Harris	ac4216b43d	Incorporated new AMO tests from riscv-arch-test	2023-10-16 10:25:45 -07:00
Limnanthes Serafini	034c289a36	Misc typo and indent fixing.	2023-04-13 16:54:15 -07:00
Limnanthes Serafini	3f9a22e8d4	Minor comments.	2023-04-12 02:57:42 -07:00
Limnanthes Serafini	095f3d5542	Added performance and distribution to sim and wrapper. Added colors too!	2023-04-12 02:54:05 -07:00
Limnanthes Serafini	e6a9d236b5	Wrapper for running CacheSim on the rv64gc suites	2023-04-11 19:29:05 -07:00